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=?utf-8?B?WkZWRXEvWjQ1dWRhY3QwbTZ3ODBaaEVZZlJHc2JJd3h6d3ZxRVZjeHJRMExR?= =?utf-8?B?d1Q4Tnowb1RUam5SYkNRaEdBM0J0UklGNHBLWTJSY3Q4Z013WWtrUEVYczlu?= =?utf-8?B?ejdvM0Rhcnd5WEpJT3FkMGQ1UEdvaVYramlVWWI1VzNqRU1KK0xtOVR4eCtB?= =?utf-8?B?aXFjaGVuMXYrT2cwUG4xeFZTU2tHY2RXSS9XYzRiZTI1a2FSOUR0b2JYOWJt?= =?utf-8?B?TjhJTFhqaGFEVHZndWZCTUVLL0ZjcjVjSkdNb2JhNUV5dVNsRitQMVh5UmU4?= =?utf-8?B?YVczamNzWE1rOTU2WjZENkdDYm9qMGJOdGdzRzM4dUJrZ3ZwL1JzYjduUkdv?= =?utf-8?B?bHBFMXdHbFJvVDI3Mk4yUUF4QTF1dnJVWEFEa1pHS2RsMTFiYmdQNmZnNFZO?= =?utf-8?B?VmlSVmVMVzUyTkxWZ1cvckVXaVJZbENaeXZoNmUraW9pVitZbmNDOENIOGZN?= =?utf-8?B?YUo0eURacVEzdmV4T0Ezdzh6VFUzQ0tFOXJtTUNNbXdjV25vQmFIdVJLTGsv?= =?utf-8?B?MUhkVktaSHpYdmRTaEk5eTFNOXFMUEhreVE3T3JGUnJpWHR3ZGZDL2Nhb3ps?= =?utf-8?B?bW5HTHdoVm9FQmV6dUc5MEZ4dXlxK0RyYWpIKzNWUTMvQWJBSW1tSTA4QnVU?= =?utf-8?B?M3VrdXJObS80b28yOXZuRERwak9BM2l2NnV2WUZ4V3ErbmY5MmFuNDJYQnBh?= =?utf-8?B?WDE3a3VFTWJ2L2E0QzkxL2JzSmY3TkRkZkY2YlFHS05kcHZ3NVhxcTRhSVpw?= =?utf-8?B?YmxxbWpTeGprWXR2KzFDcVZXdllEYTV3d2NTeTVxS1hrVjEvT0xoYzFpUENQ?= =?utf-8?B?SDlWYXZPWEZjUzdpTG5hc0JxYldQNTVqcnptWVVmQzNQdjNNYXp4Q0dCb01s?= =?utf-8?B?VktMZkFGT081NHhySzhsbHRtMjVXSjc2bk91aVRJOTZ0bTFyc0hXVDBHQnZt?= =?utf-8?B?WGhObjJhN0FiYlVYejB2VXhXa2tUSEtVeTBNTHBuZnBBbC9JQ1pybmF1Tmdm?= =?utf-8?B?L0FRTlUrd0pZWk9iSC9lcG5COFJ5Zk9EZjF6WmlQMnE4VktwY0tTaDJPM2VL?= =?utf-8?B?ZVVoWFMycGhZU2VWMnJCaFJvb0NsOENnZUE2c2ZIaXB2aUozREd1YnNDRnlu?= =?utf-8?B?aWZtMkJGTlNNQjBCbHZSSWF2RlZTNnN5bWFmQ09HbWwzMCthdmgrUkpkVzNU?= =?utf-8?B?dXFiZEI4ZU5KVHBZUGRXY2c4UFRRQjZFZjhueE9PTm81b0JsVXdoVThOQWVZ?= =?utf-8?B?WUlBeTJsZVk4bTB0MWU4VVpmdmZjN1JVNW9GWjNSQTFLaFgvck9hUTNJb1h6?= =?utf-8?B?NURGV1pWaHhVbjJVYW5wYkw3QVVLWCtDOWFjRjUrQUZjU3pzZUZ6ckt4N1o5?= =?utf-8?B?WEUwdDBJY1diN1F4anpEVlJmTVQ1bmpEQ2dDaXcxQ0JmQThZRnBOV0ZKWks1?= =?utf-8?B?eGZaaHVnbFNvV1B1OWhJU3JWcUE4M21KYVRNS0lkcnJiTWk2b0tVWHJPVFdi?= =?utf-8?B?d3h5TmNPZk1uVmV0UzFkMXpoQmlyTDJYK21Kc1pTWWg1NDlQNytPTFVsUHBC?= =?utf-8?B?dC9PMVpTNnEyUXkzNVVuSjNhd0xMSE0va2hDN2lsMkt4amFGSytlZktsbnhN?= =?utf-8?Q?6xZeIU1hYGw=3D?= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: AS8PR04MB8676.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 721e7da1-bbd7-49a7-fd23-08d994f68f1e X-MS-Exchange-CrossTenant-originalarrivaltime: 22 Oct 2021 00:54:53.3305 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: hongxing.zhu@nxp.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR04MB9048 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org PiAtLS0tLU9yaWdpbmFsIE1lc3NhZ2UtLS0tLQ0KPiBGcm9tOiBUaW0gSGFydmV5IDx0aGFydmV5 QGdhdGV3b3Jrcy5jb20+DQo+IFNlbnQ6IEZyaWRheSwgT2N0b2JlciAyMiwgMjAyMSAxMjowMCBB TQ0KPiBUbzogUmljaGFyZCBaaHUgPGhvbmd4aW5nLnpodUBueHAuY29tPg0KPiBDYzogTHVjYXMg U3RhY2ggPGwuc3RhY2hAcGVuZ3V0cm9uaXguZGU+OyBLaXNob24gVmlqYXkgQWJyYWhhbSBJDQo+ IDxraXNob25AdGkuY29tPjsgdmtvdWxAa2VybmVsLm9yZzsgUm9iIEhlcnJpbmcgPHJvYmhAa2Vy bmVsLm9yZz47DQo+IGdhbGFrQGtlcm5lbC5jcmFzaGluZy5vcmc7IFNoYXduIEd1byA8c2hhd25n dW9Aa2VybmVsLm9yZz47DQo+IGxpbnV4LXBoeUBsaXN0cy5pbmZyYWRlYWQub3JnOyBEZXZpY2Ug VHJlZSBNYWlsaW5nIExpc3QNCj4gPGRldmljZXRyZWVAdmdlci5rZXJuZWwub3JnPjsgTGludXgg QVJNIE1haWxpbmcgTGlzdA0KPiA8bGludXgtYXJtLWtlcm5lbEBsaXN0cy5pbmZyYWRlYWQub3Jn Pjsgb3BlbiBsaXN0DQo+IDxsaW51eC1rZXJuZWxAdmdlci5rZXJuZWwub3JnPjsgU2FzY2hhIEhh dWVyIDxrZXJuZWxAcGVuZ3V0cm9uaXguZGU+Ow0KPiBkbC1saW51eC1pbXggPGxpbnV4LWlteEBu eHAuY29tPg0KPiBTdWJqZWN0OiBSZTogW1BBVENIIHYzIDUvOV0gcGh5OiBmcmVlc2NhbGU6IHBj aWU6IGluaXRpYWxpemUgdGhlIGlteDggcGNpZQ0KPiBzdGFuZGFsb25lIHBoeSBkcml2ZXINCj4g DQo+IE9uIFR1ZSwgT2N0IDEyLCAyMDIxIGF0IDI6MDYgQU0gUmljaGFyZCBaaHUgPGhvbmd4aW5n LnpodUBueHAuY29tPg0KPiB3cm90ZToNCj4gPg0KPiA+IEFkZCB0aGUgc3RhbmRhbG9uZSBpLk1Y OCBQQ0llIFBIWSBkcml2ZXIuDQo+ID4gU29tZSByZXNldCBiaXRzIHNob3VsZCBiZSBtYW5pcHVs YXRlZCBiZXR3ZWVuIFBIWSBjb25maWd1cmF0aW9ucyBhbmQNCj4gPiBzdGF0dXMgY2hlY2soaW50 ZXJuYWwgUExMIGlzIGxvY2tlZCBvciBub3QpLg0KPiA+IFNvLCBkbyB0aGUgUEhZIGNvbmZpZ3Vy YXRpb24gaW4gdGhlIHBoeV9jYWxpYnJhdGUoKS4NCj4gPiBBbmQgY2hlY2sgdGhlIFBIWSBpcyBy ZWFkeSBvciBub3QgaW4gdGhlIHBoeV9pbml0KCkuDQo+ID4NCj4gPiBTaWduZWQtb2ZmLWJ5OiBS aWNoYXJkIFpodSA8aG9uZ3hpbmcuemh1QG54cC5jb20+DQo+ID4gLS0tDQo+ID4gIGRyaXZlcnMv cGh5L2ZyZWVzY2FsZS9LY29uZmlnICAgICAgICAgICAgICB8ICAgOSArDQo+ID4gIGRyaXZlcnMv cGh5L2ZyZWVzY2FsZS9NYWtlZmlsZSAgICAgICAgICAgICB8ICAgMSArDQo+ID4gIGRyaXZlcnMv cGh5L2ZyZWVzY2FsZS9waHktZnNsLWlteDhtLXBjaWUuYyB8IDIxOA0KPiA+ICsrKysrKysrKysr KysrKysrKysrKw0KPiA+ICAzIGZpbGVzIGNoYW5nZWQsIDIyOCBpbnNlcnRpb25zKCspDQo+ID4g IGNyZWF0ZSBtb2RlIDEwMDY0NCBkcml2ZXJzL3BoeS9mcmVlc2NhbGUvcGh5LWZzbC1pbXg4bS1w Y2llLmMNCj4gPg0KPiA+IGRpZmYgLS1naXQgYS9kcml2ZXJzL3BoeS9mcmVlc2NhbGUvS2NvbmZp Zw0KPiA+IGIvZHJpdmVycy9waHkvZnJlZXNjYWxlL0tjb25maWcgaW5kZXggMzIwNjMwZmZlM2Nk Li5mYjA4ZTUyNDI2MDINCj4gPiAxMDA2NDQNCj4gPiAtLS0gYS9kcml2ZXJzL3BoeS9mcmVlc2Nh bGUvS2NvbmZpZw0KPiA+ICsrKyBiL2RyaXZlcnMvcGh5L2ZyZWVzY2FsZS9LY29uZmlnDQo+ID4g QEAgLTE0LDMgKzE0LDEyIEBAIGNvbmZpZyBQSFlfTUlYRUxfTUlQSV9EUEhZDQo+ID4gICAgICAg ICBoZWxwDQo+ID4gICAgICAgICAgIEVuYWJsZSB0aGlzIHRvIGFkZCBzdXBwb3J0IGZvciB0aGUg TWl4ZWwgRFNJIFBIWSBhcyBmb3VuZA0KPiA+ICAgICAgICAgICBvbiBOWFAncyBpLk1YOCBmYW1p bHkgb2YgU09Dcy4NCj4gPiArDQo+ID4gK2NvbmZpZyBQSFlfRlNMX0lNWDhNX1BDSUUNCj4gPiAr ICAgICAgIHRyaXN0YXRlICJGcmVlc2NhbGUgaS5NWDggUENJRSBQSFkiDQo+ID4gKyAgICAgICBk ZXBlbmRzIG9uIE9GICYmIEhBU19JT01FTQ0KPiA+ICsgICAgICAgc2VsZWN0IEdFTkVSSUNfUEhZ DQo+ID4gKyAgICAgICBkZWZhdWx0IEFSQ0hfTVhDDQo+ID4gKyAgICAgICBoZWxwDQo+ID4gKyAg ICAgICAgIEVuYWJsZSB0aGlzIHRvIGFkZCBzdXBwb3J0IGZvciB0aGUgUENJRSBQSFkgYXMgZm91 bmQgb24NCj4gPiArICAgICAgICAgaS5NWDhNIGZhbWlseSBvZiBTT0NzLg0KPiA+IGRpZmYgLS1n aXQgYS9kcml2ZXJzL3BoeS9mcmVlc2NhbGUvTWFrZWZpbGUNCj4gPiBiL2RyaXZlcnMvcGh5L2Zy ZWVzY2FsZS9NYWtlZmlsZSBpbmRleCAxZDAyZTM4NjliNDUuLjU1ZDA3Yzc0MmFiMA0KPiA+IDEw MDY0NA0KPiA+IC0tLSBhL2RyaXZlcnMvcGh5L2ZyZWVzY2FsZS9NYWtlZmlsZQ0KPiA+ICsrKyBi L2RyaXZlcnMvcGh5L2ZyZWVzY2FsZS9NYWtlZmlsZQ0KPiA+IEBAIC0xLDMgKzEsNCBAQA0KPiA+ ICAjIFNQRFgtTGljZW5zZS1JZGVudGlmaWVyOiBHUEwtMi4wLW9ubHkNCj4gPiAgb2JqLSQoQ09O RklHX1BIWV9GU0xfSU1YOE1RX1VTQikgICAgICAgKz0gcGh5LWZzbC1pbXg4bXEtdXNiLm8NCj4g PiAgb2JqLSQoQ09ORklHX1BIWV9NSVhFTF9NSVBJX0RQSFkpICAgICAgKz0NCj4gcGh5LWZzbC1p bXg4LW1pcGktZHBoeS5vDQo+ID4gK29iai0kKENPTkZJR19QSFlfRlNMX0lNWDhNX1BDSUUpICAg ICAgICs9IHBoeS1mc2wtaW14OG0tcGNpZS5vDQo+ID4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvcGh5 L2ZyZWVzY2FsZS9waHktZnNsLWlteDhtLXBjaWUuYw0KPiA+IGIvZHJpdmVycy9waHkvZnJlZXNj YWxlL3BoeS1mc2wtaW14OG0tcGNpZS5jDQo+ID4gbmV3IGZpbGUgbW9kZSAxMDA2NDQNCj4gPiBp bmRleCAwMDAwMDAwMDAwMDAuLjMxN2NmNjFiZmYzNw0KPiA+IC0tLSAvZGV2L251bGwNCj4gPiAr KysgYi9kcml2ZXJzL3BoeS9mcmVlc2NhbGUvcGh5LWZzbC1pbXg4bS1wY2llLmMNCj4gPiBAQCAt MCwwICsxLDIxOCBAQA0KPiA+ICsvLyBTUERYLUxpY2Vuc2UtSWRlbnRpZmllcjogR1BMLTIuMCsN Cj4gPiArLyoNCj4gPiArICogQ29weXJpZ2h0IDIwMjEgTlhQDQo+ID4gKyAqLw0KPiA+ICsNCj4g PiArI2luY2x1ZGUgPGxpbnV4L2Nsay5oPg0KPiA+ICsjaW5jbHVkZSA8bGludXgvaW8uaD4NCj4g PiArI2luY2x1ZGUgPGxpbnV4L2lvcG9sbC5oPg0KPiA+ICsjaW5jbHVkZSA8bGludXgvZGVsYXku aD4NCj4gPiArI2luY2x1ZGUgPGxpbnV4L21mZC9zeXNjb24uaD4NCj4gPiArI2luY2x1ZGUgPGxp bnV4L21mZC9zeXNjb24vaW14Ny1pb211eGMtZ3ByLmg+DQo+ID4gKyNpbmNsdWRlIDxsaW51eC9t b2R1bGUuaD4NCj4gPiArI2luY2x1ZGUgPGxpbnV4L3BoeS9waHkuaD4NCj4gPiArI2luY2x1ZGUg PGxpbnV4L3BsYXRmb3JtX2RldmljZS5oPg0KPiA+ICsjaW5jbHVkZSA8bGludXgvcmVnbWFwLmg+ DQo+ID4gKyNpbmNsdWRlIDxsaW51eC9yZXNldC5oPg0KPiA+ICsjaW5jbHVkZSA8ZHQtYmluZGlu Z3MvcGh5L3BoeS1pbXg4LXBjaWUuaD4NCj4gPiArDQo+ID4gKyNkZWZpbmUgSU1YOE1NX1BDSUVf UEhZX0NNTl9SRUcwNjEgICAgIDB4MTg0DQo+ID4gKyNkZWZpbmUgIEFOQV9QTExfQ0xLX09VVF9U T19FWFRfSU9fRU4gIEJJVCgwKQ0KPiA+ICsjZGVmaW5lIElNWDhNTV9QQ0lFX1BIWV9DTU5fUkVH MDYyICAgICAweDE4OA0KPiA+ICsjZGVmaW5lICBBTkFfUExMX0NMS19PVVRfVE9fRVhUX0lPX1NF TCBCSVQoMykNCj4gPiArI2RlZmluZSBJTVg4TU1fUENJRV9QSFlfQ01OX1JFRzA2MyAgICAgMHgx OEMNCj4gPiArI2RlZmluZSAgQVVYX1BMTF9SRUZDTEtfU0VMX1NZU19QTEwgICAgR0VOTUFTSyg3 LCA2KQ0KPiA+ICsjZGVmaW5lIElNWDhNTV9QQ0lFX1BIWV9DTU5fUkVHMDY0ICAgICAweDE5MA0K PiA+ICsjZGVmaW5lICBBTkFfQVVYX1JYX1RYX1NFTF9UWCAgICAgICAgICBCSVQoNykNCj4gPiAr I2RlZmluZSAgQU5BX0FVWF9SWF9URVJNX0dORF9FTiAgICAgICAgICAgICAgICBCSVQoMykNCj4g PiArI2RlZmluZSAgQU5BX0FVWF9UWF9URVJNICAgICAgICAgICAgICAgQklUKDIpDQo+ID4gKyNk ZWZpbmUgSU1YOE1NX1BDSUVfUEhZX0NNTl9SRUcwNjUgICAgIDB4MTk0DQo+ID4gKyNkZWZpbmUg IEFOQV9BVVhfUlhfVEVSTSAgICAgICAgICAgICAgIChCSVQoNykgfCBCSVQoNCkpDQo+ID4gKyNk ZWZpbmUgIEFOQV9BVVhfVFhfTFZMICAgICAgICAgICAgICAgICAgICAgICAgR0VOTUFTSygzLCAw KQ0KPiA+ICsjZGVmaW5lIElNWDhNTV9QQ0lFX1BIWV9DTU5fUkVHNzUgICAgICAweDFENA0KPiA+ ICsjZGVmaW5lICBQQ0lFX1BIWV9DTU5fUkVHNzVfUExMX0RPTkUgICAweDMNCj4gPiArI2RlZmlu ZSBQQ0lFX1BIWV9UUlNWX1JFRzUgICAgICAgICAgICAgMHg0MTQNCj4gPiArI2RlZmluZSAgUENJ RV9QSFlfVFJTVl9SRUc1X0dFTjFfREVFTVAgMHgyRA0KPiA+ICsjZGVmaW5lIFBDSUVfUEhZX1RS U1ZfUkVHNiAgICAgICAgICAgICAweDQxOA0KPiA+ICsjZGVmaW5lICBQQ0lFX1BIWV9UUlNWX1JF RzZfR0VOMl9ERUVNUCAweEYNCj4gPiArDQo+ID4gKyNkZWZpbmUgSU1YOE1NX0dQUl9QQ0lFX1JF Rl9DTEtfU0VMICAgIEdFTk1BU0soMjUsIDI0KQ0KPiA+ICsjZGVmaW5lIElNWDhNTV9HUFJfUENJ RV9SRUZfQ0xLX1BMTA0KPiBGSUVMRF9QUkVQKElNWDhNTV9HUFJfUENJRV9SRUZfQ0xLX1NFTCwg MHgzKQ0KPiA+ICsjZGVmaW5lIElNWDhNTV9HUFJfUENJRV9SRUZfQ0xLX0VYVA0KPiBGSUVMRF9Q UkVQKElNWDhNTV9HUFJfUENJRV9SRUZfQ0xLX1NFTCwgMHgyKQ0KPiA+ICsjZGVmaW5lIElNWDhN TV9HUFJfUENJRV9BVVhfRU4gICAgICAgICBCSVQoMTkpDQo+ID4gKyNkZWZpbmUgSU1YOE1NX0dQ Ul9QQ0lFX0NNTl9SU1QgICAgICAgICAgICAgICAgQklUKDE4KQ0KPiA+ICsjZGVmaW5lIElNWDhN TV9HUFJfUENJRV9QT1dFUl9PRkYgICAgICBCSVQoMTcpDQo+ID4gKyNkZWZpbmUgSU1YOE1NX0dQ Ul9QQ0lFX1NTQ19FTiAgICAgICAgIEJJVCgxNikNCj4gPiArI2RlZmluZSBJTVg4TU1fR1BSX1BD SUVfUkVGX1VTRV9QQUQgICAgQklUKDkpDQo+ID4gKw0KPiA+ICtzdHJ1Y3QgaW14OF9wY2llX3Bo eSB7DQo+ID4gKyAgICAgICB1MzIgICAgICAgICAgICAgICAgICAgICByZWZjbGtfcGFkX21vZGU7 DQo+ID4gKyAgICAgICB2b2lkIF9faW9tZW0gICAgICAgICAgICAqYmFzZTsNCj4gPiArICAgICAg IHN0cnVjdCBjbGsgICAgICAgICAgICAgICpjbGs7DQo+ID4gKyAgICAgICBzdHJ1Y3QgcGh5ICAg ICAgICAgICAgICAqcGh5Ow0KPiA+ICsgICAgICAgc3RydWN0IHJlZ21hcCAgICAgICAgICAgKmlv bXV4Y19ncHI7DQo+ID4gKyAgICAgICBzdHJ1Y3QgcmVzZXRfY29udHJvbCAgICAqcmVzZXQ7DQo+ ID4gK307DQo+ID4gKw0KPiA+ICtzdGF0aWMgaW50IGlteDhfcGNpZV9waHlfaW5pdChzdHJ1Y3Qg cGh5ICpwaHkpIHsNCj4gPiArICAgICAgIGludCByZXQ7DQo+ID4gKyAgICAgICB1MzIgdmFsLCBw YWRfbW9kZTsNCj4gPiArICAgICAgIHN0cnVjdCBpbXg4X3BjaWVfcGh5ICppbXg4X3BoeSA9IHBo eV9nZXRfZHJ2ZGF0YShwaHkpOw0KPiA+ICsNCj4gPiArICAgICAgIHJlc2V0X2NvbnRyb2xfYXNz ZXJ0KGlteDhfcGh5LT5yZXNldCk7DQo+ID4gKw0KPiA+ICsgICAgICAgcmVnbWFwX3VwZGF0ZV9i aXRzKGlteDhfcGh5LT5pb211eGNfZ3ByLCBJT01VWENfR1BSMTQsDQo+ID4gKyAgICAgICAgICAg ICAgICAgICAgICAgICAgSU1YOE1NX0dQUl9QQ0lFX1JFRl9VU0VfUEFELA0KPiA+ICsgICAgICAg ICAgICAgICAgICAgICAgICAgIGlteDhfcGh5LT5yZWZjbGtfcGFkX21vZGUgPT0gMSA/DQo+IA0K PiBIaSBSaWNoYXJkLA0KPiANCj4gdXNlIHRoZSBlbnVtZXJhdGVkIHR5cGUgZm9yIHRoZSBjb21w YXJpc29uIGFib3ZlIGZvciBjbGFyaXR5Og0KPiBpbXg4X3BoeS0+cmVmY2xrX3BhZF9tb2RlID09 IElNWDhfUENJRV9SRUZDTEtfUEFEX0lOUFVUDQo+IA0KPiBBbHNvLCB0aGlzIGlzIHRoZSBjb25m aWd1cmF0aW9uIHRoYXQgbWFrZXMgbXkgaW14OG1tLXZlbmljZSBib2FyZHMgd2hpY2ggZG8NCj4g bm90IHVzZSBDTEtSRVEjIGhhbmcgd2hpbGUgd2FpdGluZyBmb3IgUEhZLiBJIGFtIHNldHRpbmcg aW4gbXkgZHQ6DQo+ICZwY2llX3BoeSB7DQo+ICAgICAgICAgZnNsLHJlZmNsay1wYWQtbW9kZSA9 IDxJTVg4X1BDSUVfUkVGQ0xLX1BBRF9JTlBVVD47DQo+ICAgICAgICAgY2xvY2tzID0gPCZjbGsg SU1YOE1NX0NMS19EVU1NWT47DQo+ICAgICAgICAgc3RhdHVzID0gIm9rYXkiOw0KPiB9Ow0KPiAN Cj4gVGhlIE5YUCBrZXJuZWwgd291ZGwgYWx3YXlzIHNldCB0aGlzIGJpdCB0byAwIHdoaWNoIG1h a2VzIG15IGJvYXJkIHdvcmsuDQo+IA0KPiBUaGUgSU1YOE1NUk0gZG9jdW1lbnRhdGlvbiBhcHBl YXJzIGluY29ycmVjdCBoZXJlOg0KPiBJT01VWENfR1BSX0dQUjE0IGJpdCA5OiBHUFJfUENJRTFf IFBIWV9JX0FVWF8gRU5fT1ZFUlJJREVfIEVOOg0KPiB7R1BSX1BDSUUxX1BIWV9JX0FVWF9FTl9P VkVSUklERV9FTiwNCj4gR1BSX1BDSUUxX1BIWV9GVU5DX0lfQVVYX0VOfQ0KPiAgMidiMDAgRXh0 ZXJuYWwgUmVmZXJlbmNlIENsb2NrIEkvTyAoZm9yIFBMTCkgRGlzYWJsZQ0KPiAgMidiMDEgRXh0 ZXJuYWwgUmVmZXJlbmNlIENsb2NrIEkvTyAoZm9yIFBMTCkgRW5hYmxlDQo+ICAyJ2IxMCBFeHRl cm5hbCBSZWZlcmVuY2UgQ2xvY2sgSS9PIChmb3IgUExMKSBEaXNhYmxlDQo+ICAyJ2IxMSBFeHRl cm5hbCBSZWZlcmVuY2UgQ2xvY2sgSS9PIChmb3IgUExMKSBvdXRwdXQgaXMgY29udHJvbGxlZCBi eSBDTEtSRVEjDQo+IA0KPiBIb3cgaXMgaXQgdGhleSBkZWZpbmUgdGhpcyBhcyBhIHNpbmdsZSBi aXQgdGhlbiBnaXZlIGRlc2NyaXB0aW9ucyBmb3INCj4gMiBiaXRzPyBTb21ldGhpbmcgaXMgd3Jv bmcgaGVyZS4NCj4gDQpbUmljaGFyZCBaaHVdIFRoZSBkZXNjcmlwdGlvbnMgYXJlIG5vdCBjb3Jy ZWN0LCBwbGVhc2UgaWdub3JlIHRoZW0uDQoNCj4gPiArICAgICAgICAgICAgICAgICAgICAgICAg ICBJTVg4TU1fR1BSX1BDSUVfUkVGX1VTRV9QQUQgOiAwKTsNCj4gPiArICAgICAgIHJlZ21hcF91 cGRhdGVfYml0cyhpbXg4X3BoeS0+aW9tdXhjX2dwciwgSU9NVVhDX0dQUjE0LA0KPiA+ICsgICAg ICAgICAgICAgICAgICAgICAgICAgIElNWDhNTV9HUFJfUENJRV9BVVhfRU4sDQo+ID4gKyAgICAg ICAgICAgICAgICAgICAgICAgICAgSU1YOE1NX0dQUl9QQ0lFX0FVWF9FTik7DQo+ID4gKyAgICAg ICByZWdtYXBfdXBkYXRlX2JpdHMoaW14OF9waHktPmlvbXV4Y19ncHIsIElPTVVYQ19HUFIxNCwN Cj4gPiArICAgICAgICAgICAgICAgICAgICAgICAgICBJTVg4TU1fR1BSX1BDSUVfUE9XRVJfT0ZG LCAwKTsNCj4gPiArICAgICAgIHJlZ21hcF91cGRhdGVfYml0cyhpbXg4X3BoeS0+aW9tdXhjX2dw ciwgSU9NVVhDX0dQUjE0LA0KPiA+ICsgICAgICAgICAgICAgICAgICAgICAgICAgIElNWDhNTV9H UFJfUENJRV9TU0NfRU4sIDApOw0KPiA+ICsNCj4gPiArICAgICAgIHJlZ21hcF91cGRhdGVfYml0 cyhpbXg4X3BoeS0+aW9tdXhjX2dwciwgSU9NVVhDX0dQUjE0LA0KPiA+ICsgICAgICAgICAgICAg ICAgICAgICAgICAgIElNWDhNTV9HUFJfUENJRV9SRUZfQ0xLX1NFTCwNCj4gPiArICAgICAgICAg ICAgICAgICAgICAgICAgICBpbXg4X3BoeS0+cmVmY2xrX3BhZF9tb2RlID09IDEgPw0KPiANCj4g aW14OF9waHktPnJlZmNsa19wYWRfbW9kZSA9PSBJTVg4X1BDSUVfUkVGQ0xLX1BBRF9JTlBVVA0K W1JpY2hhcmQgWmh1XSBHb3QgdGhhdC4gVGhhbmtzLg0KDQpCUg0KUmljaGFyZA0KPiANCj4gQmVz dCByZWdhcmRzLA0KPiANCj4gVGltDQo+IA0KPiA+ICsgICAgICAgICAgICAgICAgICAgICAgICAg IElNWDhNTV9HUFJfUENJRV9SRUZfQ0xLX0VYVCA6DQo+ID4gKyAgICAgICAgICAgICAgICAgICAg ICAgICAgSU1YOE1NX0dQUl9QQ0lFX1JFRl9DTEtfUExMKTsNCj4gPiArICAgICAgIHVzbGVlcF9y YW5nZSgxMDAsIDIwMCk7DQo+ID4gKw0KPiA+ICsgICAgICAgLyogRG8gdGhlIFBIWSBjb21tb24g YmxvY2sgcmVzZXQgKi8NCj4gPiArICAgICAgIHJlZ21hcF91cGRhdGVfYml0cyhpbXg4X3BoeS0+ aW9tdXhjX2dwciwgSU9NVVhDX0dQUjE0LA0KPiA+ICsgICAgICAgICAgICAgICAgICAgICAgICAg IElNWDhNTV9HUFJfUENJRV9DTU5fUlNULA0KPiA+ICsgICAgICAgICAgICAgICAgICAgICAgICAg IElNWDhNTV9HUFJfUENJRV9DTU5fUlNUKTsNCj4gPiArICAgICAgIHVzbGVlcF9yYW5nZSgyMDAs IDUwMCk7DQo+ID4gKw0KPiA+ICsNCj4gPiArICAgICAgIHBhZF9tb2RlID0gaW14OF9waHktPnJl ZmNsa19wYWRfbW9kZTsNCj4gPiArICAgICAgIGlmIChwYWRfbW9kZSA9PSBJTVg4X1BDSUVfUkVG Q0xLX1BBRF9JTlBVVCkgew0KPiA+ICsgICAgICAgICAgICAgICAvKiBDb25maWd1cmUgdGhlIHBh ZCBhcyBpbnB1dCAqLw0KPiA+ICsgICAgICAgICAgICAgICB2YWwgPSByZWFkbChpbXg4X3BoeS0+ YmFzZSArDQo+IElNWDhNTV9QQ0lFX1BIWV9DTU5fUkVHMDYxKTsNCj4gPiArICAgICAgICAgICAg ICAgd3JpdGVsKHZhbCAmIH5BTkFfUExMX0NMS19PVVRfVE9fRVhUX0lPX0VOLA0KPiA+ICsgICAg ICAgICAgICAgICAgICAgICAgaW14OF9waHktPmJhc2UgKw0KPiBJTVg4TU1fUENJRV9QSFlfQ01O X1JFRzA2MSk7DQo+ID4gKyAgICAgICB9IGVsc2UgaWYgKHBhZF9tb2RlID09IElNWDhfUENJRV9S RUZDTEtfUEFEX09VVFBVVCkgew0KPiA+ICsgICAgICAgICAgICAgICAvKiBDb25maWd1cmUgdGhl IFBIWSB0byBvdXRwdXQgdGhlIHJlZmNsb2NrIHZpYSBwYWQgKi8NCj4gPiArICAgICAgICAgICAg ICAgd3JpdGVsKEFOQV9QTExfQ0xLX09VVF9UT19FWFRfSU9fRU4sDQo+ID4gKyAgICAgICAgICAg ICAgICAgICAgICBpbXg4X3BoeS0+YmFzZSArDQo+IElNWDhNTV9QQ0lFX1BIWV9DTU5fUkVHMDYx KTsNCj4gPiArICAgICAgICAgICAgICAgd3JpdGVsKEFOQV9QTExfQ0xLX09VVF9UT19FWFRfSU9f U0VMLA0KPiA+ICsgICAgICAgICAgICAgICAgICAgICAgaW14OF9waHktPmJhc2UgKw0KPiBJTVg4 TU1fUENJRV9QSFlfQ01OX1JFRzA2Mik7DQo+ID4gKyAgICAgICAgICAgICAgIHdyaXRlbChBVVhf UExMX1JFRkNMS19TRUxfU1lTX1BMTCwNCj4gPiArICAgICAgICAgICAgICAgICAgICAgIGlteDhf cGh5LT5iYXNlICsNCj4gSU1YOE1NX1BDSUVfUEhZX0NNTl9SRUcwNjMpOw0KPiA+ICsgICAgICAg ICAgICAgICB2YWwgPSBBTkFfQVVYX1JYX1RYX1NFTF9UWCB8IEFOQV9BVVhfVFhfVEVSTTsNCj4g PiArICAgICAgICAgICAgICAgd3JpdGVsKHZhbCB8IEFOQV9BVVhfUlhfVEVSTV9HTkRfRU4sDQo+ ID4gKyAgICAgICAgICAgICAgICAgICAgICBpbXg4X3BoeS0+YmFzZSArDQo+IElNWDhNTV9QQ0lF X1BIWV9DTU5fUkVHMDY0KTsNCj4gPiArICAgICAgICAgICAgICAgd3JpdGVsKEFOQV9BVVhfUlhf VEVSTSB8IEFOQV9BVVhfVFhfTFZMLA0KPiA+ICsgICAgICAgICAgICAgICAgICAgICAgaW14OF9w aHktPmJhc2UgKw0KPiBJTVg4TU1fUENJRV9QSFlfQ01OX1JFRzA2NSk7DQo+ID4gKyAgICAgICB9 DQo+ID4gKw0KPiA+ICsgICAgICAgLyogVHVuZSBQSFkgZGUtZW1waGFzaXMgc2V0dGluZyB0byBw YXNzIFBDSWUgY29tcGxpYW5jZS4gKi8NCj4gPiArICAgICAgIHdyaXRlbChQQ0lFX1BIWV9UUlNW X1JFRzVfR0VOMV9ERUVNUCwNCj4gPiArICAgICAgICAgICAgICBpbXg4X3BoeS0+YmFzZSArIFBD SUVfUEhZX1RSU1ZfUkVHNSk7DQo+ID4gKyAgICAgICB3cml0ZWwoUENJRV9QSFlfVFJTVl9SRUc2 X0dFTjJfREVFTVAsDQo+ID4gKyAgICAgICAgICAgICAgaW14OF9waHktPmJhc2UgKyBQQ0lFX1BI WV9UUlNWX1JFRzYpOw0KPiA+ICsNCj4gPiArICAgICAgIHJlc2V0X2NvbnRyb2xfZGVhc3NlcnQo aW14OF9waHktPnJlc2V0KTsNCj4gPiArDQo+ID4gKyAgICAgICAvKiBQb2xsaW5nIHRvIGNoZWNr IHRoZSBwaHkgaXMgcmVhZHkgb3Igbm90LiAqLw0KPiA+ICsgICAgICAgcmV0ID0gcmVhZGxfcG9s bF90aW1lb3V0KGlteDhfcGh5LT5iYXNlICsNCj4gSU1YOE1NX1BDSUVfUEhZX0NNTl9SRUc3NSwN Cj4gPiArICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICB2YWwsIHZhbCA9PQ0KPiBQQ0lF X1BIWV9DTU5fUkVHNzVfUExMX0RPTkUsDQo+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgMTAsIDIwMDAwKTsNCj4gPiArICAgICAgIHJldHVybiByZXQ7DQo+ID4gK30NCj4gPiAr DQo+ID4gK3N0YXRpYyBpbnQgaW14OF9wY2llX3BoeV9wb3dlcl9vbihzdHJ1Y3QgcGh5ICpwaHkp IHsNCj4gPiArICAgICAgIHN0cnVjdCBpbXg4X3BjaWVfcGh5ICppbXg4X3BoeSA9IHBoeV9nZXRf ZHJ2ZGF0YShwaHkpOw0KPiA+ICsNCj4gPiArICAgICAgIHJldHVybiBjbGtfcHJlcGFyZV9lbmFi bGUoaW14OF9waHktPmNsayk7DQo+ID4gK30NCj4gPiArDQo+ID4gK3N0YXRpYyBpbnQgaW14OF9w Y2llX3BoeV9wb3dlcl9vZmYoc3RydWN0IHBoeSAqcGh5KSB7DQo+ID4gKyAgICAgICBzdHJ1Y3Qg aW14OF9wY2llX3BoeSAqaW14OF9waHkgPSBwaHlfZ2V0X2RydmRhdGEocGh5KTsNCj4gPiArDQo+ ID4gKyAgICAgICBjbGtfZGlzYWJsZV91bnByZXBhcmUoaW14OF9waHktPmNsayk7DQo+ID4gKw0K PiA+ICsgICAgICAgcmV0dXJuIDA7DQo+ID4gK30NCj4gPiArDQo+ID4gK3N0YXRpYyBjb25zdCBz dHJ1Y3QgcGh5X29wcyBpbXg4X3BjaWVfcGh5X29wcyA9IHsNCj4gPiArICAgICAgIC5pbml0ICAg ICAgICAgICA9IGlteDhfcGNpZV9waHlfaW5pdCwNCj4gPiArICAgICAgIC5wb3dlcl9vbiAgICAg ICA9IGlteDhfcGNpZV9waHlfcG93ZXJfb24sDQo+ID4gKyAgICAgICAucG93ZXJfb2ZmICAgICAg PSBpbXg4X3BjaWVfcGh5X3Bvd2VyX29mZiwNCj4gPiArICAgICAgIC5vd25lciAgICAgICAgICA9 IFRISVNfTU9EVUxFLA0KPiA+ICt9Ow0KPiA+ICsNCj4gPiArc3RhdGljIGludCBpbXg4X3BjaWVf cGh5X3Byb2JlKHN0cnVjdCBwbGF0Zm9ybV9kZXZpY2UgKnBkZXYpIHsNCj4gPiArICAgICAgIHN0 cnVjdCBwaHlfcHJvdmlkZXIgKnBoeV9wcm92aWRlcjsNCj4gPiArICAgICAgIHN0cnVjdCBkZXZp Y2UgKmRldiA9ICZwZGV2LT5kZXY7DQo+ID4gKyAgICAgICBzdHJ1Y3QgZGV2aWNlX25vZGUgKm5w ID0gZGV2LT5vZl9ub2RlOw0KPiA+ICsgICAgICAgc3RydWN0IGlteDhfcGNpZV9waHkgKmlteDhf cGh5Ow0KPiA+ICsgICAgICAgc3RydWN0IHJlc291cmNlICpyZXM7DQo+ID4gKw0KPiA+ICsgICAg ICAgaW14OF9waHkgPSBkZXZtX2t6YWxsb2MoZGV2LCBzaXplb2YoKmlteDhfcGh5KSwgR0ZQX0tF Uk5FTCk7DQo+ID4gKyAgICAgICBpZiAoIWlteDhfcGh5KQ0KPiA+ICsgICAgICAgICAgICAgICBy ZXR1cm4gLUVOT01FTTsNCj4gPiArDQo+ID4gKyAgICAgICAvKiBnZXQgUEhZIHJlZmNsayBwYWQg bW9kZSAqLw0KPiA+ICsgICAgICAgb2ZfcHJvcGVydHlfcmVhZF91MzIobnAsICJmc2wscmVmY2xr LXBhZC1tb2RlIiwNCj4gPiArICAgICAgICAgICAgICAgICAgICAgICAgICAgICZpbXg4X3BoeS0+ cmVmY2xrX3BhZF9tb2RlKTsNCj4gPiArDQo+ID4gKyAgICAgICBpbXg4X3BoeS0+Y2xrID0gZGV2 bV9jbGtfZ2V0KGRldiwgInBoeSIpOw0KPiA+ICsgICAgICAgaWYgKElTX0VSUihpbXg4X3BoeS0+ Y2xrKSkgew0KPiA+ICsgICAgICAgICAgICAgICBkZXZfZXJyKGRldiwgImZhaWxlZCB0byBnZXQg aW14IHBjaWUgcGh5IGNsb2NrXG4iKTsNCj4gPiArICAgICAgICAgICAgICAgcmV0dXJuIFBUUl9F UlIoaW14OF9waHktPmNsayk7DQo+ID4gKyAgICAgICB9DQo+ID4gKw0KPiA+ICsgICAgICAgLyog R3JhYiBHUFIgY29uZmlnIHJlZ2lzdGVyIHJhbmdlICovDQo+ID4gKyAgICAgICBpbXg4X3BoeS0+ aW9tdXhjX2dwciA9DQo+ID4gKw0KPiBzeXNjb25fcmVnbWFwX2xvb2t1cF9ieV9jb21wYXRpYmxl KCJmc2wsaW14NnEtaW9tdXhjLWdwciIpOw0KPiA+ICsgICAgICAgaWYgKElTX0VSUihpbXg4X3Bo eS0+aW9tdXhjX2dwcikpIHsNCj4gPiArICAgICAgICAgICAgICAgZGV2X2VycihkZXYsICJ1bmFi bGUgdG8gZmluZCBpb211eGMgcmVnaXN0ZXJzXG4iKTsNCj4gPiArICAgICAgICAgICAgICAgcmV0 dXJuIFBUUl9FUlIoaW14OF9waHktPmlvbXV4Y19ncHIpOw0KPiA+ICsgICAgICAgfQ0KPiA+ICsN Cj4gPiArICAgICAgIGlteDhfcGh5LT5yZXNldCA9IGRldm1fcmVzZXRfY29udHJvbF9nZXRfZXhj bHVzaXZlKGRldiwNCj4gInBjaWVwaHkiKTsNCj4gPiArICAgICAgIGlmIChJU19FUlIoaW14OF9w aHktPnJlc2V0KSkgew0KPiA+ICsgICAgICAgICAgICAgICBkZXZfZXJyKGRldiwgIkZhaWxlZCB0 byBnZXQgUENJRVBIWSByZXNldCBjb250cm9sXG4iKTsNCj4gPiArICAgICAgICAgICAgICAgcmV0 dXJuIFBUUl9FUlIoaW14OF9waHktPnJlc2V0KTsNCj4gPiArICAgICAgIH0NCj4gPiArDQo+ID4g KyAgICAgICByZXMgPSBwbGF0Zm9ybV9nZXRfcmVzb3VyY2UocGRldiwgSU9SRVNPVVJDRV9NRU0s IDApOw0KPiA+ICsgICAgICAgaW14OF9waHktPmJhc2UgPSBkZXZtX2lvcmVtYXBfcmVzb3VyY2Uo ZGV2LCByZXMpOw0KPiA+ICsgICAgICAgaWYgKElTX0VSUihpbXg4X3BoeS0+YmFzZSkpDQo+ID4g KyAgICAgICAgICAgICAgIHJldHVybiBQVFJfRVJSKGlteDhfcGh5LT5iYXNlKTsNCj4gPiArDQo+ ID4gKyAgICAgICBpbXg4X3BoeS0+cGh5ID0gZGV2bV9waHlfY3JlYXRlKGRldiwgTlVMTCwNCj4g JmlteDhfcGNpZV9waHlfb3BzKTsNCj4gPiArICAgICAgIGlmIChJU19FUlIoaW14OF9waHktPnBo eSkpDQo+ID4gKyAgICAgICAgICAgICAgIHJldHVybiBQVFJfRVJSKGlteDhfcGh5LT5waHkpOw0K PiA+ICsNCj4gPiArICAgICAgIHBoeV9zZXRfZHJ2ZGF0YShpbXg4X3BoeS0+cGh5LCBpbXg4X3Bo eSk7DQo+ID4gKw0KPiA+ICsgICAgICAgcGh5X3Byb3ZpZGVyID0gZGV2bV9vZl9waHlfcHJvdmlk ZXJfcmVnaXN0ZXIoZGV2LA0KPiA+ICsgb2ZfcGh5X3NpbXBsZV94bGF0ZSk7DQo+ID4gKw0KPiA+ ICsgICAgICAgcmV0dXJuIFBUUl9FUlJfT1JfWkVSTyhwaHlfcHJvdmlkZXIpOyB9DQo+ID4gKw0K PiA+ICtzdGF0aWMgY29uc3Qgc3RydWN0IG9mX2RldmljZV9pZCBpbXg4X3BjaWVfcGh5X29mX21h dGNoW10gPSB7DQo+ID4gKyAgICAgICB7LmNvbXBhdGlibGUgPSAiZnNsLGlteDhtbS1wY2llLXBo eSIsfSwNCj4gPiArICAgICAgIHsgfSwNCj4gPiArfTsNCj4gPiArTU9EVUxFX0RFVklDRV9UQUJM RShvZiwgaW14OF9wY2llX3BoeV9vZl9tYXRjaCk7DQo+ID4gKw0KPiA+ICtzdGF0aWMgc3RydWN0 IHBsYXRmb3JtX2RyaXZlciBpbXg4X3BjaWVfcGh5X2RyaXZlciA9IHsNCj4gPiArICAgICAgIC5w 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=?utf-8?B?ejdvM0Rhcnd5WEpJT3FkMGQ1UEdvaVYramlVWWI1VzNqRU1KK0xtOVR4eCtB?= =?utf-8?B?aXFjaGVuMXYrT2cwUG4xeFZTU2tHY2RXSS9XYzRiZTI1a2FSOUR0b2JYOWJt?= =?utf-8?B?TjhJTFhqaGFEVHZndWZCTUVLL0ZjcjVjSkdNb2JhNUV5dVNsRitQMVh5UmU4?= =?utf-8?B?YVczamNzWE1rOTU2WjZENkdDYm9qMGJOdGdzRzM4dUJrZ3ZwL1JzYjduUkdv?= =?utf-8?B?bHBFMXdHbFJvVDI3Mk4yUUF4QTF1dnJVWEFEa1pHS2RsMTFiYmdQNmZnNFZO?= =?utf-8?B?VmlSVmVMVzUyTkxWZ1cvckVXaVJZbENaeXZoNmUraW9pVitZbmNDOENIOGZN?= =?utf-8?B?YUo0eURacVEzdmV4T0Ezdzh6VFUzQ0tFOXJtTUNNbXdjV25vQmFIdVJLTGsv?= =?utf-8?B?MUhkVktaSHpYdmRTaEk5eTFNOXFMUEhreVE3T3JGUnJpWHR3ZGZDL2Nhb3ps?= =?utf-8?B?bW5HTHdoVm9FQmV6dUc5MEZ4dXlxK0RyYWpIKzNWUTMvQWJBSW1tSTA4QnVU?= =?utf-8?B?M3VrdXJObS80b28yOXZuRERwak9BM2l2NnV2WUZ4V3ErbmY5MmFuNDJYQnBh?= =?utf-8?B?WDE3a3VFTWJ2L2E0QzkxL2JzSmY3TkRkZkY2YlFHS05kcHZ3NVhxcTRhSVpw?= =?utf-8?B?YmxxbWpTeGprWXR2KzFDcVZXdllEYTV3d2NTeTVxS1hrVjEvT0xoYzFpUENQ?= =?utf-8?B?SDlWYXZPWEZjUzdpTG5hc0JxYldQNTVqcnptWVVmQzNQdjNNYXp4Q0dCb01s?= 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linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org > -----Original Message----- > From: Tim Harvey > Sent: Friday, October 22, 2021 12:00 AM > To: Richard Zhu > Cc: Lucas Stach ; Kishon Vijay Abraham I > ; vkoul@kernel.org; Rob Herring ; > galak@kernel.crashing.org; Shawn Guo ; > linux-phy@lists.infradead.org; Device Tree Mailing List > ; Linux ARM Mailing List > ; open list > ; Sascha Hauer ; > dl-linux-imx > Subject: Re: [PATCH v3 5/9] phy: freescale: pcie: initialize the imx8 pcie > standalone phy driver > > On Tue, Oct 12, 2021 at 2:06 AM Richard Zhu > wrote: > > > > Add the standalone i.MX8 PCIe PHY driver. > > Some reset bits should be manipulated between PHY configurations and > > status check(internal PLL is locked or not). > > So, do the PHY configuration in the phy_calibrate(). > > And check the PHY is ready or not in the phy_init(). > > > > Signed-off-by: Richard Zhu > > --- > > drivers/phy/freescale/Kconfig | 9 + > > drivers/phy/freescale/Makefile | 1 + > > drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 218 > > +++++++++++++++++++++ > > 3 files changed, 228 insertions(+) > > create mode 100644 drivers/phy/freescale/phy-fsl-imx8m-pcie.c > > > > diff --git a/drivers/phy/freescale/Kconfig > > b/drivers/phy/freescale/Kconfig index 320630ffe3cd..fb08e5242602 > > 100644 > > --- a/drivers/phy/freescale/Kconfig > > +++ b/drivers/phy/freescale/Kconfig > > @@ -14,3 +14,12 @@ config PHY_MIXEL_MIPI_DPHY > > help > > Enable this to add support for the Mixel DSI PHY as found > > on NXP's i.MX8 family of SOCs. > > + > > +config PHY_FSL_IMX8M_PCIE > > + tristate "Freescale i.MX8 PCIE PHY" > > + depends on OF && HAS_IOMEM > > + select GENERIC_PHY > > + default ARCH_MXC > > + help > > + Enable this to add support for the PCIE PHY as found on > > + i.MX8M family of SOCs. > > diff --git a/drivers/phy/freescale/Makefile > > b/drivers/phy/freescale/Makefile index 1d02e3869b45..55d07c742ab0 > > 100644 > > --- a/drivers/phy/freescale/Makefile > > +++ b/drivers/phy/freescale/Makefile > > @@ -1,3 +1,4 @@ > > # SPDX-License-Identifier: GPL-2.0-only > > obj-$(CONFIG_PHY_FSL_IMX8MQ_USB) += phy-fsl-imx8mq-usb.o > > obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY) += > phy-fsl-imx8-mipi-dphy.o > > +obj-$(CONFIG_PHY_FSL_IMX8M_PCIE) += phy-fsl-imx8m-pcie.o > > diff --git a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c > > b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c > > new file mode 100644 > > index 000000000000..317cf61bff37 > > --- /dev/null > > +++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c > > @@ -0,0 +1,218 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > +/* > > + * Copyright 2021 NXP > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +#define IMX8MM_PCIE_PHY_CMN_REG061 0x184 > > +#define ANA_PLL_CLK_OUT_TO_EXT_IO_EN BIT(0) > > +#define IMX8MM_PCIE_PHY_CMN_REG062 0x188 > > +#define ANA_PLL_CLK_OUT_TO_EXT_IO_SEL BIT(3) > > +#define IMX8MM_PCIE_PHY_CMN_REG063 0x18C > > +#define AUX_PLL_REFCLK_SEL_SYS_PLL GENMASK(7, 6) > > +#define IMX8MM_PCIE_PHY_CMN_REG064 0x190 > > +#define ANA_AUX_RX_TX_SEL_TX BIT(7) > > +#define ANA_AUX_RX_TERM_GND_EN BIT(3) > > +#define ANA_AUX_TX_TERM BIT(2) > > +#define IMX8MM_PCIE_PHY_CMN_REG065 0x194 > > +#define ANA_AUX_RX_TERM (BIT(7) | BIT(4)) > > +#define ANA_AUX_TX_LVL GENMASK(3, 0) > > +#define IMX8MM_PCIE_PHY_CMN_REG75 0x1D4 > > +#define PCIE_PHY_CMN_REG75_PLL_DONE 0x3 > > +#define PCIE_PHY_TRSV_REG5 0x414 > > +#define PCIE_PHY_TRSV_REG5_GEN1_DEEMP 0x2D > > +#define PCIE_PHY_TRSV_REG6 0x418 > > +#define PCIE_PHY_TRSV_REG6_GEN2_DEEMP 0xF > > + > > +#define IMX8MM_GPR_PCIE_REF_CLK_SEL GENMASK(25, 24) > > +#define IMX8MM_GPR_PCIE_REF_CLK_PLL > FIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL, 0x3) > > +#define IMX8MM_GPR_PCIE_REF_CLK_EXT > FIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL, 0x2) > > +#define IMX8MM_GPR_PCIE_AUX_EN BIT(19) > > +#define IMX8MM_GPR_PCIE_CMN_RST BIT(18) > > +#define IMX8MM_GPR_PCIE_POWER_OFF BIT(17) > > +#define IMX8MM_GPR_PCIE_SSC_EN BIT(16) > > +#define IMX8MM_GPR_PCIE_REF_USE_PAD BIT(9) > > + > > +struct imx8_pcie_phy { > > + u32 refclk_pad_mode; > > + void __iomem *base; > > + struct clk *clk; > > + struct phy *phy; > > + struct regmap *iomuxc_gpr; > > + struct reset_control *reset; > > +}; > > + > > +static int imx8_pcie_phy_init(struct phy *phy) { > > + int ret; > > + u32 val, pad_mode; > > + struct imx8_pcie_phy *imx8_phy = phy_get_drvdata(phy); > > + > > + reset_control_assert(imx8_phy->reset); > > + > > + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, > > + IMX8MM_GPR_PCIE_REF_USE_PAD, > > + imx8_phy->refclk_pad_mode == 1 ? > > Hi Richard, > > use the enumerated type for the comparison above for clarity: > imx8_phy->refclk_pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT > > Also, this is the configuration that makes my imx8mm-venice boards which do > not use CLKREQ# hang while waiting for PHY. I am setting in my dt: > &pcie_phy { > fsl,refclk-pad-mode = ; > clocks = <&clk IMX8MM_CLK_DUMMY>; > status = "okay"; > }; > > The NXP kernel woudl always set this bit to 0 which makes my board work. > > The IMX8MMRM documentation appears incorrect here: > IOMUXC_GPR_GPR14 bit 9: GPR_PCIE1_ PHY_I_AUX_ EN_OVERRIDE_ EN: > {GPR_PCIE1_PHY_I_AUX_EN_OVERRIDE_EN, > GPR_PCIE1_PHY_FUNC_I_AUX_EN} > 2'b00 External Reference Clock I/O (for PLL) Disable > 2'b01 External Reference Clock I/O (for PLL) Enable > 2'b10 External Reference Clock I/O (for PLL) Disable > 2'b11 External Reference Clock I/O (for PLL) output is controlled by CLKREQ# > > How is it they define this as a single bit then give descriptions for > 2 bits? Something is wrong here. > [Richard Zhu] The descriptions are not correct, please ignore them. > > + IMX8MM_GPR_PCIE_REF_USE_PAD : 0); > > + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, > > + IMX8MM_GPR_PCIE_AUX_EN, > > + IMX8MM_GPR_PCIE_AUX_EN); > > + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, > > + IMX8MM_GPR_PCIE_POWER_OFF, 0); > > + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, > > + IMX8MM_GPR_PCIE_SSC_EN, 0); > > + > > + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, > > + IMX8MM_GPR_PCIE_REF_CLK_SEL, > > + imx8_phy->refclk_pad_mode == 1 ? > > imx8_phy->refclk_pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT [Richard Zhu] Got that. Thanks. BR Richard > > Best regards, > > Tim > > > + IMX8MM_GPR_PCIE_REF_CLK_EXT : > > + IMX8MM_GPR_PCIE_REF_CLK_PLL); > > + usleep_range(100, 200); > > + > > + /* Do the PHY common block reset */ > > + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, > > + IMX8MM_GPR_PCIE_CMN_RST, > > + IMX8MM_GPR_PCIE_CMN_RST); > > + usleep_range(200, 500); > > + > > + > > + pad_mode = imx8_phy->refclk_pad_mode; > > + if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT) { > > + /* Configure the pad as input */ > > + val = readl(imx8_phy->base + > IMX8MM_PCIE_PHY_CMN_REG061); > > + writel(val & ~ANA_PLL_CLK_OUT_TO_EXT_IO_EN, > > + imx8_phy->base + > IMX8MM_PCIE_PHY_CMN_REG061); > > + } else if (pad_mode == IMX8_PCIE_REFCLK_PAD_OUTPUT) { > > + /* Configure the PHY to output the refclock via pad */ > > + writel(ANA_PLL_CLK_OUT_TO_EXT_IO_EN, > > + imx8_phy->base + > IMX8MM_PCIE_PHY_CMN_REG061); > > + writel(ANA_PLL_CLK_OUT_TO_EXT_IO_SEL, > > + imx8_phy->base + > IMX8MM_PCIE_PHY_CMN_REG062); > > + writel(AUX_PLL_REFCLK_SEL_SYS_PLL, > > + imx8_phy->base + > IMX8MM_PCIE_PHY_CMN_REG063); > > + val = ANA_AUX_RX_TX_SEL_TX | ANA_AUX_TX_TERM; > > + writel(val | ANA_AUX_RX_TERM_GND_EN, > > + imx8_phy->base + > IMX8MM_PCIE_PHY_CMN_REG064); > > + writel(ANA_AUX_RX_TERM | ANA_AUX_TX_LVL, > > + imx8_phy->base + > IMX8MM_PCIE_PHY_CMN_REG065); > > + } > > + > > + /* Tune PHY de-emphasis setting to pass PCIe compliance. */ > > + writel(PCIE_PHY_TRSV_REG5_GEN1_DEEMP, > > + imx8_phy->base + PCIE_PHY_TRSV_REG5); > > + writel(PCIE_PHY_TRSV_REG6_GEN2_DEEMP, > > + imx8_phy->base + PCIE_PHY_TRSV_REG6); > > + > > + reset_control_deassert(imx8_phy->reset); > > + > > + /* Polling to check the phy is ready or not. */ > > + ret = readl_poll_timeout(imx8_phy->base + > IMX8MM_PCIE_PHY_CMN_REG75, > > + val, val == > PCIE_PHY_CMN_REG75_PLL_DONE, > > + 10, 20000); > > + return ret; > > +} > > + > > +static int imx8_pcie_phy_power_on(struct phy *phy) { > > + struct imx8_pcie_phy *imx8_phy = phy_get_drvdata(phy); > > + > > + return clk_prepare_enable(imx8_phy->clk); > > +} > > + > > +static int imx8_pcie_phy_power_off(struct phy *phy) { > > + struct imx8_pcie_phy *imx8_phy = phy_get_drvdata(phy); > > + > > + clk_disable_unprepare(imx8_phy->clk); > > + > > + return 0; > > +} > > + > > +static const struct phy_ops imx8_pcie_phy_ops = { > > + .init = imx8_pcie_phy_init, > > + .power_on = imx8_pcie_phy_power_on, > > + .power_off = imx8_pcie_phy_power_off, > > + .owner = THIS_MODULE, > > +}; > > + > > +static int imx8_pcie_phy_probe(struct platform_device *pdev) { > > + struct phy_provider *phy_provider; > > + struct device *dev = &pdev->dev; > > + struct device_node *np = dev->of_node; > > + struct imx8_pcie_phy *imx8_phy; > > + struct resource *res; > > + > > + imx8_phy = devm_kzalloc(dev, sizeof(*imx8_phy), GFP_KERNEL); > > + if (!imx8_phy) > > + return -ENOMEM; > > + > > + /* get PHY refclk pad mode */ > > + of_property_read_u32(np, "fsl,refclk-pad-mode", > > + &imx8_phy->refclk_pad_mode); > > + > > + imx8_phy->clk = devm_clk_get(dev, "phy"); > > + if (IS_ERR(imx8_phy->clk)) { > > + dev_err(dev, "failed to get imx pcie phy clock\n"); > > + return PTR_ERR(imx8_phy->clk); > > + } > > + > > + /* Grab GPR config register range */ > > + imx8_phy->iomuxc_gpr = > > + > syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); > > + if (IS_ERR(imx8_phy->iomuxc_gpr)) { > > + dev_err(dev, "unable to find iomuxc registers\n"); > > + return PTR_ERR(imx8_phy->iomuxc_gpr); > > + } > > + > > + imx8_phy->reset = devm_reset_control_get_exclusive(dev, > "pciephy"); > > + if (IS_ERR(imx8_phy->reset)) { > > + dev_err(dev, "Failed to get PCIEPHY reset control\n"); > > + return PTR_ERR(imx8_phy->reset); > > + } > > + > > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > > + imx8_phy->base = devm_ioremap_resource(dev, res); > > + if (IS_ERR(imx8_phy->base)) > > + return PTR_ERR(imx8_phy->base); > > + > > + imx8_phy->phy = devm_phy_create(dev, NULL, > &imx8_pcie_phy_ops); > > + if (IS_ERR(imx8_phy->phy)) > > + return PTR_ERR(imx8_phy->phy); > > + > > + phy_set_drvdata(imx8_phy->phy, imx8_phy); > > + > > + phy_provider = devm_of_phy_provider_register(dev, > > + of_phy_simple_xlate); > > + > > + return PTR_ERR_OR_ZERO(phy_provider); } > > + > > +static const struct of_device_id imx8_pcie_phy_of_match[] = { > > + {.compatible = "fsl,imx8mm-pcie-phy",}, > > + { }, > > +}; > > +MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match); > > + > > +static struct platform_driver imx8_pcie_phy_driver = { > > + .probe = imx8_pcie_phy_probe, > > + .driver = { > > + .name = "imx8-pcie-phy", > > + .of_match_table = imx8_pcie_phy_of_match, > > + } > > +}; > > +module_platform_driver(imx8_pcie_phy_driver); > > + > > +MODULE_DESCRIPTION("FSL IMX8 PCIE PHY driver"); > > +MODULE_LICENSE("GPL"); > > -- > > 2.25.1 > > -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EEEC4C433EF for ; Fri, 22 Oct 2021 00:56:30 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9B09E6135E for ; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org > -----Original Message----- > From: Tim Harvey > Sent: Friday, October 22, 2021 12:00 AM > To: Richard Zhu > Cc: Lucas Stach ; Kishon Vijay Abraham I > ; vkoul@kernel.org; Rob Herring ; > galak@kernel.crashing.org; Shawn Guo ; > linux-phy@lists.infradead.org; Device Tree Mailing List > ; Linux ARM Mailing List > ; open list > ; Sascha Hauer ; > dl-linux-imx > Subject: Re: [PATCH v3 5/9] phy: freescale: pcie: initialize the imx8 pcie > standalone phy driver > > On Tue, Oct 12, 2021 at 2:06 AM Richard Zhu > wrote: > > > > Add the standalone i.MX8 PCIe PHY driver. > > Some reset bits should be manipulated between PHY configurations and > > status check(internal PLL is locked or not). > > So, do the PHY configuration in the phy_calibrate(). > > And check the PHY is ready or not in the phy_init(). > > > > Signed-off-by: Richard Zhu > > --- > > drivers/phy/freescale/Kconfig | 9 + > > drivers/phy/freescale/Makefile | 1 + > > drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 218 > > +++++++++++++++++++++ > > 3 files changed, 228 insertions(+) > > create mode 100644 drivers/phy/freescale/phy-fsl-imx8m-pcie.c > > > > diff --git a/drivers/phy/freescale/Kconfig > > b/drivers/phy/freescale/Kconfig index 320630ffe3cd..fb08e5242602 > > 100644 > > --- a/drivers/phy/freescale/Kconfig > > +++ b/drivers/phy/freescale/Kconfig > > @@ -14,3 +14,12 @@ config PHY_MIXEL_MIPI_DPHY > > help > > Enable this to add support for the Mixel DSI PHY as found > > on NXP's i.MX8 family of SOCs. > > + > > +config PHY_FSL_IMX8M_PCIE > > + tristate "Freescale i.MX8 PCIE PHY" > > + depends on OF && HAS_IOMEM > > + select GENERIC_PHY > > + default ARCH_MXC > > + help > > + Enable this to add support for the PCIE PHY as found on > > + i.MX8M family of SOCs. > > diff --git a/drivers/phy/freescale/Makefile > > b/drivers/phy/freescale/Makefile index 1d02e3869b45..55d07c742ab0 > > 100644 > > --- a/drivers/phy/freescale/Makefile > > +++ b/drivers/phy/freescale/Makefile > > @@ -1,3 +1,4 @@ > > # SPDX-License-Identifier: GPL-2.0-only > > obj-$(CONFIG_PHY_FSL_IMX8MQ_USB) += phy-fsl-imx8mq-usb.o > > obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY) += > phy-fsl-imx8-mipi-dphy.o > > +obj-$(CONFIG_PHY_FSL_IMX8M_PCIE) += phy-fsl-imx8m-pcie.o > > diff --git a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c > > b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c > > new file mode 100644 > > index 000000000000..317cf61bff37 > > --- /dev/null > > +++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c > > @@ -0,0 +1,218 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > +/* > > + * Copyright 2021 NXP > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +#define IMX8MM_PCIE_PHY_CMN_REG061 0x184 > > +#define ANA_PLL_CLK_OUT_TO_EXT_IO_EN BIT(0) > > +#define IMX8MM_PCIE_PHY_CMN_REG062 0x188 > > +#define ANA_PLL_CLK_OUT_TO_EXT_IO_SEL BIT(3) > > +#define IMX8MM_PCIE_PHY_CMN_REG063 0x18C > > +#define AUX_PLL_REFCLK_SEL_SYS_PLL GENMASK(7, 6) > > +#define IMX8MM_PCIE_PHY_CMN_REG064 0x190 > > +#define ANA_AUX_RX_TX_SEL_TX BIT(7) > > +#define ANA_AUX_RX_TERM_GND_EN BIT(3) > > +#define ANA_AUX_TX_TERM BIT(2) > > +#define IMX8MM_PCIE_PHY_CMN_REG065 0x194 > > +#define ANA_AUX_RX_TERM (BIT(7) | BIT(4)) > > +#define ANA_AUX_TX_LVL GENMASK(3, 0) > > +#define IMX8MM_PCIE_PHY_CMN_REG75 0x1D4 > > +#define PCIE_PHY_CMN_REG75_PLL_DONE 0x3 > > +#define PCIE_PHY_TRSV_REG5 0x414 > > +#define PCIE_PHY_TRSV_REG5_GEN1_DEEMP 0x2D > > +#define PCIE_PHY_TRSV_REG6 0x418 > > +#define PCIE_PHY_TRSV_REG6_GEN2_DEEMP 0xF > > + > > +#define IMX8MM_GPR_PCIE_REF_CLK_SEL GENMASK(25, 24) > > +#define IMX8MM_GPR_PCIE_REF_CLK_PLL > FIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL, 0x3) > > +#define IMX8MM_GPR_PCIE_REF_CLK_EXT > FIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL, 0x2) > > +#define IMX8MM_GPR_PCIE_AUX_EN BIT(19) > > +#define IMX8MM_GPR_PCIE_CMN_RST BIT(18) > > +#define IMX8MM_GPR_PCIE_POWER_OFF BIT(17) > > +#define IMX8MM_GPR_PCIE_SSC_EN BIT(16) > > +#define IMX8MM_GPR_PCIE_REF_USE_PAD BIT(9) > > + > > +struct imx8_pcie_phy { > > + u32 refclk_pad_mode; > > + void __iomem *base; > > + struct clk *clk; > > + struct phy *phy; > > + struct regmap *iomuxc_gpr; > > + struct reset_control *reset; > > +}; > > + > > +static int imx8_pcie_phy_init(struct phy *phy) { > > + int ret; > > + u32 val, pad_mode; > > + struct imx8_pcie_phy *imx8_phy = phy_get_drvdata(phy); > > + > > + reset_control_assert(imx8_phy->reset); > > + > > + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, > > + IMX8MM_GPR_PCIE_REF_USE_PAD, > > + imx8_phy->refclk_pad_mode == 1 ? > > Hi Richard, > > use the enumerated type for the comparison above for clarity: > imx8_phy->refclk_pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT > > Also, this is the configuration that makes my imx8mm-venice boards which do > not use CLKREQ# hang while waiting for PHY. I am setting in my dt: > &pcie_phy { > fsl,refclk-pad-mode = ; > clocks = <&clk IMX8MM_CLK_DUMMY>; > status = "okay"; > }; > > The NXP kernel woudl always set this bit to 0 which makes my board work. > > The IMX8MMRM documentation appears incorrect here: > IOMUXC_GPR_GPR14 bit 9: GPR_PCIE1_ PHY_I_AUX_ EN_OVERRIDE_ EN: > {GPR_PCIE1_PHY_I_AUX_EN_OVERRIDE_EN, > GPR_PCIE1_PHY_FUNC_I_AUX_EN} > 2'b00 External Reference Clock I/O (for PLL) Disable > 2'b01 External Reference Clock I/O (for PLL) Enable > 2'b10 External Reference Clock I/O (for PLL) Disable > 2'b11 External Reference Clock I/O (for PLL) output is controlled by CLKREQ# > > How is it they define this as a single bit then give descriptions for > 2 bits? Something is wrong here. > [Richard Zhu] The descriptions are not correct, please ignore them. > > + IMX8MM_GPR_PCIE_REF_USE_PAD : 0); > > + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, > > + IMX8MM_GPR_PCIE_AUX_EN, > > + IMX8MM_GPR_PCIE_AUX_EN); > > + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, > > + IMX8MM_GPR_PCIE_POWER_OFF, 0); > > + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, > > + IMX8MM_GPR_PCIE_SSC_EN, 0); > > + > > + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, > > + IMX8MM_GPR_PCIE_REF_CLK_SEL, > > + imx8_phy->refclk_pad_mode == 1 ? > > imx8_phy->refclk_pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT [Richard Zhu] Got that. Thanks. BR Richard > > Best regards, > > Tim > > > + IMX8MM_GPR_PCIE_REF_CLK_EXT : > > + IMX8MM_GPR_PCIE_REF_CLK_PLL); > > + usleep_range(100, 200); > > + > > + /* Do the PHY common block reset */ > > + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, > > + IMX8MM_GPR_PCIE_CMN_RST, > > + IMX8MM_GPR_PCIE_CMN_RST); > > + usleep_range(200, 500); > > + > > + > > + pad_mode = imx8_phy->refclk_pad_mode; > > + if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT) { > > + /* Configure the pad as input */ > > + val = readl(imx8_phy->base + > IMX8MM_PCIE_PHY_CMN_REG061); > > + writel(val & ~ANA_PLL_CLK_OUT_TO_EXT_IO_EN, > > + imx8_phy->base + > IMX8MM_PCIE_PHY_CMN_REG061); > > + } else if (pad_mode == IMX8_PCIE_REFCLK_PAD_OUTPUT) { > > + /* Configure the PHY to output the refclock via pad */ > > + writel(ANA_PLL_CLK_OUT_TO_EXT_IO_EN, > > + imx8_phy->base + > IMX8MM_PCIE_PHY_CMN_REG061); > > + writel(ANA_PLL_CLK_OUT_TO_EXT_IO_SEL, > > + imx8_phy->base + > IMX8MM_PCIE_PHY_CMN_REG062); > > + writel(AUX_PLL_REFCLK_SEL_SYS_PLL, > > + imx8_phy->base + > IMX8MM_PCIE_PHY_CMN_REG063); > > + val = ANA_AUX_RX_TX_SEL_TX | ANA_AUX_TX_TERM; > > + writel(val | ANA_AUX_RX_TERM_GND_EN, > > + imx8_phy->base + > IMX8MM_PCIE_PHY_CMN_REG064); > > + writel(ANA_AUX_RX_TERM | ANA_AUX_TX_LVL, > > + imx8_phy->base + > IMX8MM_PCIE_PHY_CMN_REG065); > > + } > > + > > + /* Tune PHY de-emphasis setting to pass PCIe compliance. */ > > + writel(PCIE_PHY_TRSV_REG5_GEN1_DEEMP, > > + imx8_phy->base + PCIE_PHY_TRSV_REG5); > > + writel(PCIE_PHY_TRSV_REG6_GEN2_DEEMP, > > + imx8_phy->base + PCIE_PHY_TRSV_REG6); > > + > > + reset_control_deassert(imx8_phy->reset); > > + > > + /* Polling to check the phy is ready or not. */ > > + ret = readl_poll_timeout(imx8_phy->base + > IMX8MM_PCIE_PHY_CMN_REG75, > > + val, val == > PCIE_PHY_CMN_REG75_PLL_DONE, > > + 10, 20000); > > + return ret; > > +} > > + > > +static int imx8_pcie_phy_power_on(struct phy *phy) { > > + struct imx8_pcie_phy *imx8_phy = phy_get_drvdata(phy); > > + > > + return clk_prepare_enable(imx8_phy->clk); > > +} > > + > > +static int imx8_pcie_phy_power_off(struct phy *phy) { > > + struct imx8_pcie_phy *imx8_phy = phy_get_drvdata(phy); > > + > > + clk_disable_unprepare(imx8_phy->clk); > > + > > + return 0; > > +} > > + > > +static const struct phy_ops imx8_pcie_phy_ops = { > > + .init = imx8_pcie_phy_init, > > + .power_on = imx8_pcie_phy_power_on, > > + .power_off = imx8_pcie_phy_power_off, > > + .owner = THIS_MODULE, > > +}; > > + > > +static int imx8_pcie_phy_probe(struct platform_device *pdev) { > > + struct phy_provider *phy_provider; > > + struct device *dev = &pdev->dev; > > + struct device_node *np = dev->of_node; > > + struct imx8_pcie_phy *imx8_phy; > > + struct resource *res; > > + > > + imx8_phy = devm_kzalloc(dev, sizeof(*imx8_phy), GFP_KERNEL); > > + if (!imx8_phy) > > + return -ENOMEM; > > + > > + /* get PHY refclk pad mode */ > > + of_property_read_u32(np, "fsl,refclk-pad-mode", > > + &imx8_phy->refclk_pad_mode); > > + > > + imx8_phy->clk = devm_clk_get(dev, "phy"); > > + if (IS_ERR(imx8_phy->clk)) { > > + dev_err(dev, "failed to get imx pcie phy clock\n"); > > + return PTR_ERR(imx8_phy->clk); > > + } > > + > > + /* Grab GPR config register range */ > > + imx8_phy->iomuxc_gpr = > > + > syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); > > + if (IS_ERR(imx8_phy->iomuxc_gpr)) { > > + dev_err(dev, "unable to find iomuxc registers\n"); > > + return PTR_ERR(imx8_phy->iomuxc_gpr); > > + } > > + > > + imx8_phy->reset = devm_reset_control_get_exclusive(dev, > "pciephy"); > > + if (IS_ERR(imx8_phy->reset)) { > > + dev_err(dev, "Failed to get PCIEPHY reset control\n"); > > + return PTR_ERR(imx8_phy->reset); > > + } > > + > > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > > + imx8_phy->base = devm_ioremap_resource(dev, res); > > + if (IS_ERR(imx8_phy->base)) > > + return PTR_ERR(imx8_phy->base); > > + > > + imx8_phy->phy = devm_phy_create(dev, NULL, > &imx8_pcie_phy_ops); > > + if (IS_ERR(imx8_phy->phy)) > > + return PTR_ERR(imx8_phy->phy); > > + > > + phy_set_drvdata(imx8_phy->phy, imx8_phy); > > + > > + phy_provider = devm_of_phy_provider_register(dev, > > + of_phy_simple_xlate); > > + > > + return PTR_ERR_OR_ZERO(phy_provider); } > > + > > +static const struct of_device_id imx8_pcie_phy_of_match[] = { > > + {.compatible = "fsl,imx8mm-pcie-phy",}, > > + { }, > > +}; > > +MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match); > > + > > +static struct platform_driver imx8_pcie_phy_driver = { > > + .probe = imx8_pcie_phy_probe, > > + .driver = { > > + .name = "imx8-pcie-phy", > > + .of_match_table = imx8_pcie_phy_of_match, > > + } > > +}; > > +module_platform_driver(imx8_pcie_phy_driver); > > + > > +MODULE_DESCRIPTION("FSL IMX8 PCIE PHY driver"); > > +MODULE_LICENSE("GPL"); > > -- > > 2.25.1 > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel