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=?utf-8?B?dGhJRXFFSGZObDA1ZUlDT1MyT0g2MWFXZVdvR1NjYnlzVHhhNjRUVmZ5SUoy?= =?utf-8?B?ZzVLYkN6L1FZRnZOcE5UNStmcWZFbkE2NWdoYVdwL2dTTDJwcTVWanh2b0Fn?= =?utf-8?B?Tm5qNzFEYzh1UEFYbnQzQjVHUFF4YlZRL1NUcDc3Qk9sTHU0SThlRWRiNlAv?= =?utf-8?B?bU8yZHFtbzVvaStiVG9RWTVVME53V1IxYVZGZTZwczdqbDdZb3lyV1RJc04x?= =?utf-8?B?RVR4d0UwYmlwQ1hSemFuZGhqcE1pUWlTZ1JQS3FQVEhSajM5VkdVNGgvNGZw?= =?utf-8?B?UGtDUGdseXVkTDRadi9SaUpnZmhKZE5WeTRnZm9SbGd5eGd5QmdIc2xzV2tL?= =?utf-8?B?aGIzTXlEc3ZPNWppMWtrb2J1cDVvNTh6amt4V2NzbnY3RVJMYjlPWkYxUGlG?= =?utf-8?B?MGd6REJEV1QzNkh6Z0xncmFMWGxJTVFqOTAvNCtCc2pnSk1vSVR3akludzR3?= =?utf-8?B?UGFvbG9ISXV3V1NXL2NzWVVKcmNOMlFLa2VsamN6Nnoxa25pZytYSlFTYTlT?= =?utf-8?B?M2lsMU9GeVRCb1V0eVdrbHRLNXpXeHRrY0dCdEppY3hVYmhGZkNrSFhkK0pV?= =?utf-8?B?UWd1SFhFL1lnbFJ5eTVNT0M4UTd4MWI3N0xkQ28vMUhra2VlbEJSeXNFSEEr?= =?utf-8?B?ODZKdzcxbFo0ZnpYUW1jVHVnMG5rZDdnSDFwZys1MENMVWFORWg5VTZYOXdQ?= =?utf-8?B?WVl5SjFmSEo4OHBiNmVmNXZPYzdXcU15SU85cEdjMnA2U3krdGo5bXhHWWE2?= =?utf-8?B?dHNxRGNZUGVlbWlIQTllQXRRQWYxS1hXV3NxODM2Rkd2VDlaZjRHU05RNmFS?= =?utf-8?B?ZnJNdVMvVEx2NW5TL09odHg2dFl6VE5icTI3dDVxbUU3MnZrNHFGdlQyQTFQ?= =?utf-8?B?SkZBc0haSTFhMGtRYlFJbCtRSEhkaXRpUU1UR2Q1RVdZeW9BL2MrZWF6bHIv?= =?utf-8?B?YTd6SzJ3U1BrNVh2b0ovSktHV2ZFeGJ4T2tyUG95TEpKNE13dHhqS1NHdXl5?= =?utf-8?B?RmpNNThDWm9QVXBIVlYybGtpSENjOHcyZEpzZTVDNU9rUC9kdjNuTU55RSts?= =?utf-8?B?dzM5K3I1LzUxeWxXV2RDTjd6dmhFQXM4WitoQkZwUHNTVFlVQmkrUTJpTDhx?= =?utf-8?B?elNLY3NKV3RvcGhjT2lmMXZVdHYyU3JmRjRBZ0Y3UmpRR21RZ0pkZ25UUkNq?= =?utf-8?B?VGVUNnU5SzRxMTVMZm5OWWU3Z0QvZmNOejN1WDh3dlNWc0Q2UTFOQmZObStW?= =?utf-8?B?bHp2RGdnOXM2RFlYejQ0Tytra051dGhkd09hQXZOU093TVFJOFFiUzBTcm45?= =?utf-8?B?TGI3U2R0S1IvUFhBanNDejVqMXc2NTZoNTFwbkZqbmRuYkNqUDdmbmJhWWFT?= =?utf-8?B?MkkyUklOZTdiUzlKS1BnanIwNWRJeDUyY2ROcXg0SzZCQmIxUms0QzFVWFli?= =?utf-8?B?UlkwN2JhRlE1cFZQSUhHWEUrV1ZaK0g1bm5oTEM1TG1CMG8zYWVQYkR6ODlm?= =?utf-8?B?UkdlK09KWURWaGpoSzlhQjRCWXkrUHE4aGhheWUzQ2RUbzQ4STFMU094YlZM?= =?utf-8?B?elk5RjVoMk9USTZVSnlzQU9FOFRIRWdMeHkzaisvU2kzMGNpZXJkS0x0d25o?= =?utf-8?B?SjRiRlQzZGRocldQY3hWSlBwZU5aZG5kT2hyZ1RPekpGZytHdW1QcEVlWXhn?= =?utf-8?B?Qy9JaDBncllJTUxUazNjL0lUL1pZM2N1WWtMc21Selk3UG15NWxkTzNZcHBJ?= =?utf-8?B?MUlFRE1Jd0hsTCtWalBTVFgzY0k1bTN5TFRwRzVpcnprNGpVMFFBZ2VwZktN?= =?utf-8?B?OUdvNEU5S1JZVXkxY2JGNnc2S0srRWxuUE1JanBqUDMxV1NYR25pVUJGNXQr?= =?utf-8?B?NUE9PQ==?= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: AS8PR04MB8676.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4ab4055c-f78f-4e9d-bc3a-08d9975cf471 X-MS-Exchange-CrossTenant-originalarrivaltime: 25 Oct 2021 02:12:54.2311 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: ONHCKATasdF1ZyAcvcbWDEhkDPfGgxYb88qj98uPQQUsROiyc3l4DYpav4IzfX2uLuVLYsC7XNn3jtVu05i6bg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR04MB8994 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org DQo+IC0tLS0tT3JpZ2luYWwgTWVzc2FnZS0tLS0tDQo+IEZyb206IFRpbSBIYXJ2ZXkgPHRoYXJ2 ZXlAZ2F0ZXdvcmtzLmNvbT4NCj4gU2VudDogU2F0dXJkYXksIE9jdG9iZXIgMjMsIDIwMjEgMTI6 NTUgQU0NCj4gVG86IFJpY2hhcmQgWmh1IDxob25neGluZy56aHVAbnhwLmNvbT4NCj4gQ2M6IEx1 Y2FzIFN0YWNoIDxsLnN0YWNoQHBlbmd1dHJvbml4LmRlPjsgS2lzaG9uIFZpamF5IEFicmFoYW0g SQ0KPiA8a2lzaG9uQHRpLmNvbT47IHZrb3VsQGtlcm5lbC5vcmc7IFJvYiBIZXJyaW5nIDxyb2Jo QGtlcm5lbC5vcmc+Ow0KPiBnYWxha0BrZXJuZWwuY3Jhc2hpbmcub3JnOyBTaGF3biBHdW8gPHNo YXduZ3VvQGtlcm5lbC5vcmc+Ow0KPiBsaW51eC1waHlAbGlzdHMuaW5mcmFkZWFkLm9yZzsgRGV2 aWNlIFRyZWUgTWFpbGluZyBMaXN0DQo+IDxkZXZpY2V0cmVlQHZnZXIua2VybmVsLm9yZz47IExp bnV4IEFSTSBNYWlsaW5nIExpc3QNCj4gPGxpbnV4LWFybS1rZXJuZWxAbGlzdHMuaW5mcmFkZWFk Lm9yZz47IG9wZW4gbGlzdA0KPiA8bGludXgta2VybmVsQHZnZXIua2VybmVsLm9yZz47IFNhc2No YSBIYXVlciA8a2VybmVsQHBlbmd1dHJvbml4LmRlPjsNCj4gZGwtbGludXgtaW14IDxsaW51eC1p bXhAbnhwLmNvbT4NCj4gU3ViamVjdDogUmU6IFtQQVRDSCB2MyAwLzldIGFkZCB0aGUgaW14OG0g cGNpZSBwaHkgZHJpdmVyIGFuZCBpbXg4bW0gcGNpZQ0KPiBzdXBwb3J0DQo+IA0KPiBPbiBGcmks IE9jdCAyMiwgMjAyMSBhdCA4OjU5IEFNIFRpbSBIYXJ2ZXkgPHRoYXJ2ZXlAZ2F0ZXdvcmtzLmNv bT4NCj4gd3JvdGU6DQo+ID4NCj4gPiBPbiBUaHUsIE9jdCAyMSwgMjAyMSBhdCA1OjQzIFBNIFJp Y2hhcmQgWmh1IDxob25neGluZy56aHVAbnhwLmNvbT4NCj4gd3JvdGU6DQo+ID4gPg0KPiA+ID4g PiAtLS0tLU9yaWdpbmFsIE1lc3NhZ2UtLS0tLQ0KPiA+ID4gPiBGcm9tOiBUaW0gSGFydmV5IDx0 aGFydmV5QGdhdGV3b3Jrcy5jb20+DQo+ID4gPiA+IFNlbnQ6IEZyaWRheSwgT2N0b2JlciAyMiwg MjAyMSAxMjoyNSBBTQ0KPiA+ID4gPiBUbzogUmljaGFyZCBaaHUgPGhvbmd4aW5nLnpodUBueHAu Y29tPg0KPiA+ID4gPiBDYzogTHVjYXMgU3RhY2ggPGwuc3RhY2hAcGVuZ3V0cm9uaXguZGU+OyBL aXNob24gVmlqYXkgQWJyYWhhbSBJDQo+ID4gPiA+IDxraXNob25AdGkuY29tPjsgdmtvdWxAa2Vy bmVsLm9yZzsgUm9iIEhlcnJpbmcgPHJvYmhAa2VybmVsLm9yZz47DQo+ID4gPiA+IGdhbGFrQGtl cm5lbC5jcmFzaGluZy5vcmc7IFNoYXduIEd1byA8c2hhd25ndW9Aa2VybmVsLm9yZz47DQo+ID4g PiA+IGxpbnV4LXBoeUBsaXN0cy5pbmZyYWRlYWQub3JnOyBEZXZpY2UgVHJlZSBNYWlsaW5nIExp c3QNCj4gPiA+ID4gPGRldmljZXRyZWVAdmdlci5rZXJuZWwub3JnPjsgTGludXggQVJNIE1haWxp bmcgTGlzdA0KPiA+ID4gPiA8bGludXgtYXJtLWtlcm5lbEBsaXN0cy5pbmZyYWRlYWQub3JnPjsg b3BlbiBsaXN0DQo+ID4gPiA+IDxsaW51eC1rZXJuZWxAdmdlci5rZXJuZWwub3JnPjsgU2FzY2hh IEhhdWVyDQo+ID4gPiA+IDxrZXJuZWxAcGVuZ3V0cm9uaXguZGU+OyBkbC1saW51eC1pbXggPGxp bnV4LWlteEBueHAuY29tPg0KPiA+ID4gPiBTdWJqZWN0OiBSZTogW1BBVENIIHYzIDAvOV0gYWRk IHRoZSBpbXg4bSBwY2llIHBoeSBkcml2ZXIgYW5kDQo+ID4gPiA+IGlteDhtbSBwY2llIHN1cHBv cnQNCj4gPiA+ID4NCj4gPiA+ID4gT24gV2VkLCBPY3QgMjAsIDIwMjEgYXQgODozMiBQTSBSaWNo YXJkIFpodSA8aG9uZ3hpbmcuemh1QG54cC5jb20+DQo+ID4gPiA+IHdyb3RlOg0KPiA+ID4gPiA+ DQo+ID4gPiA+ID4gPHNuaXBwZWQuLi4+DQo+ID4gPiA+ID4gPg0KPiA+ID4gPiA+ID4gUmljaGFy ZCwNCj4gPiA+ID4gPiA+DQo+ID4gPiA+ID4gPiBXaGF0IGlzIHRoaXMgJ2ludmFsaWQgcmVzb3Vy Y2UnIGFib3V0PyBJIHNlZSB0aGF0IHdpdGggbXkNCj4gPiA+ID4gPiA+IGRvd25zdHJlYW0gSU1Y OE1NIFBDSWUgZHJpdmVyIGFzIHdlbGwgYW5kIGhhdmUgYmVlbiBhc2tlZA0KPiBhYm91dCBpdC4N Cj4gPiA+ID4gPiA+DQo+ID4gPiA+ID4gW1JpY2hhcmQgWmh1XSBIaSBUaW06DQo+ID4gPiA+ID4g VGhpcyBjb21wbGFpbiBpcyBjYXVzZWQgYnkgdGhlIGZvbGxvd2luZyBjb2RlcyBpbiBwY2llLWRl c2lnbndhcmUuYw0KPiBkcml2ZXIuDQo+ID4gPiA+ID4gSSdtIG5vdCBzdXJlIHRoYXQgd2h5IHRo ZXJlIGlzIG9ubHkgc2l6ZSBhc3NpZ25tZW50IGFmdGVyIHRoZQ0KPiA+ID4gPiA+IHJlcyB2YWxp ZCBjaGVjaywNCj4gPiA+ID4gYW5kIGRvIG5vdGhpbmcgaWYgdGhlIHJlcyBpcyBpbnZhbGlkLg0K PiA+ID4gPiA+IEl0IHNlZW1zIHRoYXQgaXQgaXMgYW4gZXhwZWN0ZWQgZGVzaWduIGxvZ2ljIHJl ZmVyIHRvIHRoZSBsYXRlciBjb2Rlcy4NCj4gPiA+ID4gPiAgICAgICAgICAgICAgICAgaWYgKCFw Y2ktPmF0dV9iYXNlKSB7DQo+ID4gPiA+ID4gICAgICAgICAgICAgICAgICAgICAgICAgc3RydWN0 IHJlc291cmNlICpyZXMgPQ0KPiA+ID4gPiA+DQo+ID4gPiA+IHBsYXRmb3JtX2dldF9yZXNvdXJj ZV9ieW5hbWUocGRldiwgSU9SRVNPVVJDRV9NRU0sICJhdHUiKTsNCj4gPiA+ID4gPiAgICAgICAg ICAgICAgICAgICAgICAgICBpZiAocmVzKQ0KPiA+ID4gPiA+ICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgcGNpLT5hdHVfc2l6ZSA9DQo+IHJlc291cmNlX3NpemUocmVzKTsNCj4gPiA+ ID4gPiAgICAgICAgICAgICAgICAgICAgICAgICBwY2ktPmF0dV9iYXNlID0NCj4gPiA+ID4gZGV2 bV9pb3JlbWFwX3Jlc291cmNlKGRldiwgcmVzKTsNCj4gPiA+ID4gPiAgICAgICAgICAgICAgICAg ICAgICAgICBpZiAoSVNfRVJSKHBjaS0+YXR1X2Jhc2UpKQ0KPiA+ID4gPiA+ICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgcGNpLT5hdHVfYmFzZSA9DQo+IHBjaS0+ZGJpX2Jhc2UgKw0K PiA+ID4gPiBERUZBVUxUX0RCSV9BVFVfT0ZGU0VUOw0KPiA+ID4gPiA+ICAgICAgICAgICAgICAg ICB9DQo+ID4gPiA+ID4NCj4gPiA+ID4gPiBTaW5jZSB0aGUgZGVmYXVsdCBvZmZzZXQgaXMgdXNl ZCBvbiBpLk1YOE1NLCB0aGUgImF0dSIgaXMgbm90DQo+ID4gPiA+ID4gc3BlY2lmaWVkIGluDQo+ ID4gPiA+IGkuTVg4TU0gUENJZSBEVCBub2RlLCBzbyB0aGVyZSBpcyBubyByZWFsIHJlcyBhdCBh bGwuDQo+ID4gPiA+ID4gVGhlbiwgZGV2bV9pb3JlbWFwX3Jlc291cmNlKCkgd291bGQgY29tcGxh aW4gdGhlIGludmFsaWQgcmVzb3VyY2UuDQo+ID4gPiA+DQo+ID4gPiA+IEkgdGhpbmsgeW91IGFy ZSBzYXlpbmcgYSBjaGFuZ2Ugc2hvdWxkIGJlIG1hZGUgbGlrZSB0aGlzOg0KPiA+ID4gPiBkaWZm IC0tZ2l0IGEvZHJpdmVycy9wY2kvY29udHJvbGxlci9kd2MvcGNpZS1kZXNpZ253YXJlLmMNCj4g PiA+ID4gYi9kcml2ZXJzL3BjaS9jb250cm9sbGVyL2R3Yy9wY2llLWRlc2lnbndhcmUuYw0KPiA+ ID4gPiBpbmRleCBhOTQ1ZjBjMGU3M2QuLjMyNTRmNjBkMTcxMyAxMDA2NDQNCj4gPiA+ID4gLS0t IGEvZHJpdmVycy9wY2kvY29udHJvbGxlci9kd2MvcGNpZS1kZXNpZ253YXJlLmMNCj4gPiA+ID4g KysrIGIvZHJpdmVycy9wY2kvY29udHJvbGxlci9kd2MvcGNpZS1kZXNpZ253YXJlLmMNCj4gPiA+ ID4gQEAgLTY3MSwxMCArNjcxLDExIEBAIHZvaWQgZHdfcGNpZV9pYXR1X2RldGVjdChzdHJ1Y3Qg ZHdfcGNpZQ0KPiAqcGNpKQ0KPiA+ID4gPiAgICAgICAgICAgICAgICAgaWYgKCFwY2ktPmF0dV9i YXNlKSB7DQo+ID4gPiA+ICAgICAgICAgICAgICAgICAgICAgICAgIHN0cnVjdCByZXNvdXJjZSAq cmVzID0NCj4gPiA+ID4NCj4gPiA+ID4gcGxhdGZvcm1fZ2V0X3Jlc291cmNlX2J5bmFtZShwZGV2 LA0KPiA+ID4gPiBJT1JFU09VUkNFX01FTSwgImF0dSIpOw0KPiA+ID4gPiAtICAgICAgICAgICAg ICAgICAgICAgICBpZiAocmVzKQ0KPiA+ID4gPiArICAgICAgICAgICAgICAgICAgICAgICBpZiAo cmVzKSB7DQo+ID4gPiA+ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgcGNpLT5hdHVf c2l6ZSA9DQo+IHJlc291cmNlX3NpemUocmVzKTsNCj4gPiA+ID4gLSAgICAgICAgICAgICAgICAg ICAgICAgcGNpLT5hdHVfYmFzZSA9DQo+IGRldm1faW9yZW1hcF9yZXNvdXJjZShkZXYsDQo+ID4g PiA+IHJlcyk7DQo+ID4gPiA+IC0gICAgICAgICAgICAgICAgICAgICAgIGlmIChJU19FUlIocGNp LT5hdHVfYmFzZSkpDQo+ID4gPiA+ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgcGNp LT5hdHVfYmFzZSA9DQo+ID4gPiA+IGRldm1faW9yZW1hcF9yZXNvdXJjZShkZXYsIHJlcyk7DQo+ ID4gPiA+ICsgICAgICAgICAgICAgICAgICAgICAgIH0NCj4gPiA+ID4gKyAgICAgICAgICAgICAg ICAgICAgICAgaWYgKCFwY2ktPmF0dV9iYXNlIHx8DQo+ID4gPiA+ICsgSVNfRVJSKHBjaS0+YXR1 X2Jhc2UpKQ0KPiA+ID4gPiAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIHBjaS0+YXR1 X2Jhc2UgPSBwY2ktPmRiaV9iYXNlDQo+ICsNCj4gPiA+ID4gREVGQVVMVF9EQklfQVRVX09GRlNF VDsNCj4gPiA+ID4gICAgICAgICAgICAgICAgIH0NCj4gPiA+ID4NCj4gPiA+ID4gc28gdGhhdCBp dCBsb29rcyBsaWtlIHRoaXM6DQo+ID4gPiA+ICAgICAgICAgICAgICAgICBpZiAoIXBjaS0+YXR1 X2Jhc2UpIHsNCj4gPiA+ID4gICAgICAgICAgICAgICAgICAgICAgICAgc3RydWN0IHJlc291cmNl ICpyZXMgPQ0KPiA+ID4gPg0KPiA+ID4gPiBwbGF0Zm9ybV9nZXRfcmVzb3VyY2VfYnluYW1lKHBk ZXYsDQo+ID4gPiA+IElPUkVTT1VSQ0VfTUVNLCAiYXR1Iik7DQo+ID4gPiA+ICAgICAgICAgICAg ICAgICAgICAgICAgIGlmIChyZXMpIHsNCj4gPiA+ID4gICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICBwY2ktPmF0dV9zaXplID0NCj4gcmVzb3VyY2Vfc2l6ZShyZXMpOw0KPiA+ID4gPiAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIHBjaS0+YXR1X2Jhc2UgPQ0KPiA+ID4gPiBk ZXZtX2lvcmVtYXBfcmVzb3VyY2UoZGV2LCByZXMpOw0KPiA+ID4gPiAgICAgICAgICAgICAgICAg ICAgICAgICB9DQo+ID4gPiA+ICAgICAgICAgICAgICAgICAgICAgICAgIGlmICghcGNpLT5hdHVf YmFzZSB8fA0KPiBJU19FUlIocGNpLT5hdHVfYmFzZSkpDQo+ID4gPiA+ICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgcGNpLT5hdHVfYmFzZSA9IHBjaS0+ZGJpX2Jhc2UNCj4gKw0KPiA+ ID4gPiBERUZBVUxUX0RCSV9BVFVfT0ZGU0VUOw0KPiA+ID4gPiAgICAgICAgICAgICAgICAgfQ0K PiA+ID4gPg0KPiA+ID4gPiBSaWdodD8NCj4gPiA+IFtSaWNoYXJkIFpodV0gWWVzLCBpdCBpcy4g VGhlIHJlcyBzaG91bGRuJ3QgYmUgcmVtYXBwZWQgaWYgaXQgaXMgaW52YWxpZA0KPiByZXNvdXJj ZSBtZW1vcnkuDQo+ID4NCj4gPiBPaywgSSB3aWxsIHN1Ym1pdCBhIHBhdGNoIGZvciB0aGF0Lg0K PiA+DQpbUmljaGFyZCBaaHVdIFRoYW5rcyBmb3IgeW91ciBoZWxwLiBQbGVhc2UgY2MgbWUsIGlm IHlvdSBpc3N1ZSB0aGF0IHBhdGNoLg0KDQo+ID4gPg0KPiA+ID4gPg0KPiA+ID4gPiA+DQo+ID4g PiA+ID4gPiA+IFsgICAgMS4zMTYzMDVdIGlteDZxLXBjaWUgMzM4MDAwMDAucGNpZTogaUFUVSB1 bnJvbGw6IGVuYWJsZWQNCj4gPiA+ID4gPiA+ID4gWyAgICAxLjMyMTc5OV0gaW14NnEtcGNpZSAz MzgwMDAwMC5wY2llOiBEZXRlY3RlZCBpQVRVIHJlZ2lvbnM6DQo+IDQNCj4gPiA+ID4gPiA+IG91 dGJvdW5kLCA0IGluYm91bmQNCj4gPiA+ID4gPiA+ID4gWyAgICAxLjQyOTgwM10gaW14NnEtcGNp ZSAzMzgwMDAwMC5wY2llOiBMaW5rIHVwDQo+ID4gPiA+ID4gPiA+IFsgICAgMS41MzQ0OTddIGlt eDZxLXBjaWUgMzM4MDAwMDAucGNpZTogTGluayB1cA0KPiA+ID4gPiA+ID4gPiBbICAgIDEuNTM4 ODcwXSBpbXg2cS1wY2llIDMzODAwMDAwLnBjaWU6IExpbmsgdXAsIEdlbjINCj4gPiA+ID4gPiA+ ID4gWyAgICAxLjU1MDM2NF0gaW14NnEtcGNpZSAzMzgwMDAwMC5wY2llOiBMaW5rIHVwDQo+ID4g PiA+ID4gPiA+IFsgICAgMS41NTA0ODddIGlteDZxLXBjaWUgMzM4MDAwMDAucGNpZTogUENJIGhv c3QgYnJpZGdlIHRvIGJ1cw0KPiA+ID4gPiAwMDAwOjAwDQo+ID4gPiA+ID4gPiA+IFsgICAgMS41 NjU1NDVdIHBjaV9idXMgMDAwMDowMDogcm9vdCBidXMgcmVzb3VyY2UgW2J1cyAwMC1mZl0NCj4g PiA+ID4gPiA+ID4gWyAgICAxLjU3MzgzNF0gcGNpX2J1cyAwMDAwOjAwOiByb290IGJ1cyByZXNv dXJjZSBbaW8NCj4gMHgwMDAwLTB4ZmZmZl0NCj4gPiA+ID4gPiA+ID4gWyAgICAxLjU4MDA1NV0g cGNpX2J1cyAwMDAwOjAwOiByb290IGJ1cyByZXNvdXJjZSBbbWVtDQo+ID4gPiA+ID4gPiAweDE4 MDAwMDAwLTB4MWZlZmZmZmZdDQo+ID4gPiA+ID4gPiA+IFsgICAgMS41ODY5NjhdIHBjaSAwMDAw OjAwOjAwLjA6IFsxNmMzOmFiY2RdIHR5cGUgMDEgY2xhc3MNCj4gMHgwNjA0MDANCj4gPiA+ID4g PiA+ID4gWyAgICAxLjU5Mjk5N10gcGNpIDAwMDA6MDA6MDAuMDogcmVnIDB4MTA6IFttZW0NCj4g PiA+ID4gMHgwMDAwMDAwMC0weDAwMGZmZmZmXQ0KPiA+ID4gPiA+ID4gPiBbICAgIDEuNTk5Mjgy XSBwY2kgMDAwMDowMDowMC4wOiByZWcgMHgzODogW21lbQ0KPiA+ID4gPiAweDAwMDAwMDAwLTB4 MDAwMGZmZmYNCj4gPiA+ID4gPiA+IHByZWZdDQo+ID4gPiA+ID4gPiA+IFsgICAgMS42MDYwMzNd IHBjaSAwMDAwOjAwOjAwLjA6IHN1cHBvcnRzIEQxDQo+ID4gPiA+ID4gPiA+IFsgICAgMS42MTAw NTNdIHBjaSAwMDAwOjAwOjAwLjA6IFBNRSMgc3VwcG9ydGVkIGZyb20gRDAgRDENCj4gRDNob3QN Cj4gPiA+ID4gPiA+IEQzY29sZA0KPiA+ID4gPiA+ID4gPiBbICAgIDEuNjE4MjA2XSBwY2kgMDAw MDowMTowMC4wOiBbMTViNzo1MDAyXSB0eXBlIDAwIGNsYXNzDQo+IDB4MDEwODAyDQo+ID4gPiA+ ID4gPiA+IFsgICAgMS42MjQyOTNdIHBjaSAwMDAwOjAxOjAwLjA6IHJlZyAweDEwOiBbbWVtDQo+ ID4gPiA+IDB4MDAwMDAwMDAtMHgwMDAwM2ZmZg0KPiA+ID4gPiA+ID4gNjRiaXRdDQo+ID4gPiA+ ID4gPiA+IFsgICAgMS42MzExNzddIHBjaSAwMDAwOjAxOjAwLjA6IHJlZyAweDIwOiBbbWVtDQo+ ID4gPiA+IDB4MDAwMDAwMDAtMHgwMDAwMDBmZg0KPiA+ID4gPiA+ID4gNjRiaXRdDQo+ID4gPiA+ ID4gPiA+IFsgICAgMS42Mzg0MDldIHBjaSAwMDAwOjAxOjAwLjA6IDQuMDAwIEdiL3MgYXZhaWxh YmxlIFBDSWUNCj4gYmFuZHdpZHRoLA0KPiA+ID4gPiA+ID4gbGltaXRlZCBieSA1LjAgR1QvcyBQ Q0llIHgxIGxpbmsgYXQgMDAwMDowMDowMC4wIChjYXBhYmxlIG9mDQo+ID4gPiA+ID4gPiAzMS41 MDQgR2IvcyB3aXRoDQo+ID4gPiA+ID4gPiA4LjAgR1QvcyBQQ0llIHg0IGxpbmspDQo+ID4gPiA+ ID4gPiA+IFsgICAgMS42NjQ5MzFdIHBjaSAwMDAwOjAwOjAwLjA6IEJBUiAwOiBhc3NpZ25lZCBb bWVtDQo+ID4gPiA+ID4gPiAweDE4MDAwMDAwLTB4MTgwZmZmZmZdDQo+ID4gPiA+ID4gPiA+IFsg ICAgMS42NzE3NDVdIHBjaSAwMDAwOjAwOjAwLjA6IEJBUiAxNDogYXNzaWduZWQgW21lbQ0KPiA+ ID4gPiA+ID4gMHgxODEwMDAwMC0weDE4MWZmZmZmXQ0KPiA+ID4gPiA+ID4gPiBbICAgIDEuNjc4 NjM0XSBwY2kgMDAwMDowMDowMC4wOiBCQVIgNjogYXNzaWduZWQgW21lbQ0KPiA+ID4gPiA+ID4g MHgxODIwMDAwMC0weDE4MjBmZmZmIHByZWZdDQo+ID4gPiA+ID4gPiA+IFsgICAgMS42ODU4NzNd IHBjaSAwMDAwOjAxOjAwLjA6IEJBUiAwOiBhc3NpZ25lZCBbbWVtDQo+ID4gPiA+ID4gPiAweDE4 MTAwMDAwLTB4MTgxMDNmZmYgNjRiaXRdDQo+ID4gPiA+ID4gPiA+IFsgICAgMS42OTMyMjJdIHBj aSAwMDAwOjAxOjAwLjA6IEJBUiA0OiBhc3NpZ25lZCBbbWVtDQo+ID4gPiA+ID4gPiAweDE4MTA0 MDAwLTB4MTgxMDQwZmYgNjRiaXRdDQo+ID4gPiA+ID4gPiA+IFsgICAgMS43MDA1NzddIHBjaSAw MDAwOjAwOjAwLjA6IFBDSSBicmlkZ2UgdG8gW2J1cyAwMS1mZl0NCj4gPiA+ID4gPiA+ID4gWyAg ICAxLjcwNTgxNF0gcGNpIDAwMDA6MDA6MDAuMDogICBicmlkZ2Ugd2luZG93IFttZW0NCj4gPiA+ ID4gPiA+IDB4MTgxMDAwMDAtMHgxODFmZmZmZl0NCj4gPiA+ID4gPiA+ID4gWyAgICAxLjcxMjk3 Ml0gcGNpZXBvcnQgMDAwMDowMDowMC4wOiBQTUU6IFNpZ25hbGluZyB3aXRoIElSUQ0KPiAyMTYN Cj4gPiA+ID4gPiA+ID4gIg0KPiA+ID4gPiA+ID4gPiBSZWdhcmRpbmcgdGhlIGxvZyB5b3UgcGFz dGVkLCBpdCBzZWVtcyB0aGF0IHRoZSBjbG9jayBpcyBub3QNCj4gPiA+ID4gPiA+ID4gZmVlZCB0 byBQSFkNCj4gPiA+ID4gPiA+IHByb3Blcmx5Lg0KPiA+ID4gPiA+ID4gPg0KPiA+ID4gPiA+ID4g PiBBbnl3YXksIGxldCdzIHdhaXRpbmcgZm9yIHRoZSB2NCBzZXJpZXMsIHRoZW4gbWFrZSBhIHRy eS4NCj4gPiA+ID4gPiA+ID4gVGhhbmtzIGZvciB5b3VyDQo+ID4gPiA+ID4gPiBncmVhdCBoZWxw IHRvIG1ha2UgdGhlIGRvdWJsZSB0ZXN0cy4NCj4gPiA+ID4gPiA+ID4NCj4gPiA+ID4gPiA+DQo+ ID4gPiA+ID4gPiBNeSBib2FyZHMgZG8gbm90IHVzZSBDTEtSRVEjIHNvIEkgZG8gbm90IGhhdmUg dGhhdCBkZWZpbmVkIGluDQo+ID4gPiA+ID4gPiBwaW5tdXggYW5kIEkgZm91bmQgdGhhdCBpZiBJ IGFkZA0KPiA+ID4gPiA+ID4gTVg4TU1fSU9NVVhDX0kyQzRfU0NMX1BDSUUxX0NMS1JFUV9CDQo+ ID4gPiA+IFBDSWUNCj4gPiA+ID4gPiA+IHdvcmtzIG9uIG15IGJvYXJkIGJ1dCB0aGlzIGlzbid0 IGEgc29sdXRpb24ganVzdCBhIHdvcmstYXJvdW5kDQo+ID4gPiA+ID4gPiAoSSBoYXZlIGJvYXJk cyB0aGF0IHVzZSB0aGUgb25seSB0d28gcG9zc2libGUgcGlucyBmb3IgQ0xLUkVRDQo+ID4gPiA+ ID4gPiBhcyBvdGhlcg0KPiA+ID4gPiBmZWF0dXJlcykuDQo+ID4gPiA+ID4gPg0KPiA+ID4gPiA+ ID4gU2ltaWxhcmx5IHlvdSB3aWxsIGZpbmQgb24gdGhlIGlteDhtbS1ldmsgaWYgeW91IGNvbW1l bnQgb3V0DQo+ID4gPiA+ID4gPiB0aGUgQ0xLUkVRICh3aGljaCBpc24ndCByZXF1aXJlZCkgdGhl IGlteDhtbWV2ayB3aWxsIGVuZCB1cA0KPiA+ID4gPiA+ID4gaGFuZ2luZyBsaWtlIG15DQo+ID4g PiA+IGJvYXJkczoNCj4gPiA+ID4gPiBbUmljaGFyZCBaaHVdIEhpIFRpbToNCj4gPiA+ID4gPiBS ZWdhcmRpbmcgdGhlIFNQRUMsIHRoZSBDTEtSRVEjIGlzIG1hbmRhdG9yeSByZXF1aXJlZCwgYW5k DQo+ID4gPiA+ID4gc2hvdWxkIGJlDQo+ID4gPiA+IGNvbmZpZ3VyZWQgYXMgYW4gb3BlbiBkcmFp biwgYWN0aXZlIGxvdyBzaWduYWwuDQo+ID4gPiA+ID4gQW5kIHRoaXMgc2lnbmFsIHNob3VsZCBi ZSBkcml2ZW4gbG93IGJ5IHRoZSBQQ0llIE0uMiBkZXZpY2UgdG8NCj4gPiA+ID4gPiByZXF1ZXN0 IHRoZQ0KPiA+ID4gPiBSRUYgY2xvY2sgYmUgYXZhaWxhYmxlKGFjdGl2ZSBsb3cpLg0KPiA+ID4g PiA+IFNvLCB0aGVyZSBpcyBzdWNoIGtpbmQgb2YgQ0xLUkVRIyBwaW4gZGVmaW5pdGlvbiBvbiBp Lk1YOE1NIEVWSw0KPiBib2FyZC4NCj4gPiA+ID4gPg0KPiA+ID4gPiA+IEFueXdheSwgSSB0aGlu ayB0aGUgZXh0ZXJuYWwgT1NDIGNpcmN1aXQgc2hvdWxkIGJlIGFsd2F5cw0KPiA+ID4gPiA+IHJ1 bm5pbmcgaWYgdGhlcmUgaXMNCj4gPiA+ID4gbm8gQ0xLUkVRIyBvbiB5b3VyIEhXIGJvYXJkIGRl c2lnbi4NCj4gPiA+ID4gPg0KPiA+ID4gPg0KPiA+ID4gPiBUaGUgd2F5IEkgdW5kZXJzdGFuZCBp dCBpcyBDTEtSRVEjIGFsbG93cyB0aGUgaG9zdCB0byBkaXNhYmxlIHRoZQ0KPiA+ID4gPiBSRUZD TEsgd2hlbiBub3QgbmVlZGVkIGZvciBwb3dlciBzYXZpbmdzIHNvIGl0IHdvdWxkIHNlZW0gb3B0 aW9uYWwNCj4gPiA+ID4gdG8gaW1wbGVtZW50IHRoYXQgYW5kIGlmIG5vdCBpbXBsZW1lbnRlZCBz aG91bGQgYmUgbGVmdCB1bmNvbm5lY3RlZCBvbg0KPiB0aGUgY2FyZC4NCj4gPiA+ID4NCj4gPiA+ IFtSaWNoYXJkIFpodV0gTm8sIG5vdCB0aGF0IHdheS4gUmVnYXJkaW5nIHRoZSBTUEVDLCB0aGlz IHNpZ25hbCBpcw0KPiBtYW5kYXRvcnkgcmVxdWlyZWQuDQo+ID4gPiBFc3BlY2lhbGx5IGZvciB0 aGUgTDFzcyB1c2FnZXMuIFRoaXMgc2lnbmFsIHdvdWxkIGJlIE9EKG9wZW4gZHJhaW4pLA0KPiA+ ID4gYmktZGlyZWN0aW9uYWwsIGFuZCBtaWdodCBiZSBkcml2ZW4gbG93L2hpZ2ggYnkgUkMgb3Ig RVAgYXV0b21hdGljYWxseSBpZg0KPiBMMXNzIG1vZGVzIGFyZSBlbmFibGVkLg0KPiA+ID4gWW91 IGNhbiBtYWtlIHJlZmVyZW5jZSB0byB0aGUNCj4gPiA+ICJFQ05fTDFfUE1fU3Vic3RhdGVzX3dp dGhfQ0xLUkVRXzMxX01heV8yMDEzX1JldjEwYSIsIG9yIHRoZQ0KPiBjaGFwdGVyIDUuNSBMMSBQ TSBTdWJzdGF0ZXMgb2YgIlBDSSBFeHByZXNzIEJhc2UgU3BlY2lmaWNhdGlvbiwgUmV2LiA0LjAN Cj4gVmVyc2lvbiAxLjAiLg0KPiA+ID4NCj4gPg0KPiA+IENMS1JFUSBpcyBvbmx5IG1hbmRhdG9y eSBpZiB5b3Ugd2lzaCB0byBzdXBwb3J0IGNsb2NrIHBvd2VyDQo+ID4gbWFuYWdlbWVudC4gTWFu eSBib2FyZHMgd2l0aCBhIFBDSSBob3N0IGNvbnRyb2xsZXIgZG8gbm90IHN1cHBvcnQNCj4gPiB0 aGlzLg0KW1JpY2hhcmQgWmh1XSBPa2F5LCB1bmRlcnN0b29kLg0KDQo+ID4NCj4gPiA+ID4gPiA+ IGRpZmYgLS1naXQgYS9hcmNoL2FybTY0L2Jvb3QvZHRzL2ZyZWVzY2FsZS9pbXg4bW0tZXZrLmR0 c2kNCj4gPiA+ID4gPiA+IGIvYXJjaC9hcm02NC9ib290L2R0cy9mcmVlc2NhbGUvaW14OG1tLWV2 ay5kdHNpDQo+ID4gPiA+ID4gPiBpbmRleCA1Y2U0M2RhYTBjOGIuLmYwMDIzYjQ4ZjQ3NSAxMDA2 NDQNCj4gPiA+ID4gPiA+IC0tLSBhL2FyY2gvYXJtNjQvYm9vdC9kdHMvZnJlZXNjYWxlL2lteDht bS1ldmsuZHRzaQ0KPiA+ID4gPiA+ID4gKysrIGIvYXJjaC9hcm02NC9ib290L2R0cy9mcmVlc2Nh bGUvaW14OG1tLWV2ay5kdHNpDQo+ID4gPiA+ID4gPiBAQCAtNDQ4LDcgKzQ0OCw5IEBADQo+ID4g PiA+ID4gPg0KPiA+ID4gPiA+ID4gICAgICAgICBwaW5jdHJsX3BjaWUwOiBwY2llMGdycCB7DQo+ ID4gPiA+ID4gPiAgICAgICAgICAgICAgICAgZnNsLHBpbnMgPSA8DQo+ID4gPiA+ID4gPiArLyoN Cj4gPiA+ID4gPiA+DQo+ID4gPiA+ID4gPiBNWDhNTV9JT01VWENfSTJDNF9TQ0xfUENJRTFfQ0xL UkVRX0IgICAgMHg2MQ0KPiA+ID4gPiA+ID4gKyovDQo+ID4gPiA+ID4gPg0KPiA+ID4gPiBNWDhN TV9JT01VWENfU0FJMl9SWEZTX0dQSU80X0lPMjENCj4gPiA+ID4gPiA+IDB4NDENCj4gPiA+ID4g PiA+ICAgICAgICAgICAgICAgICA+Ow0KPiA+ID4gPiA+ID4gICAgICAgICB9Ow0KPiA+ID4gPiA+ ID4NCj4gPiA+ID4gPiA+IEkgaGF2ZSBQQ0llIHdvcmtpbmcgd2l0aCBhIGRyaXZlciB0aGF0IEkg cG9ydGVkIGZyb20gTlhQJ3MNCj4gPiA+ID4gPiA+IGtlcm5lbCB3aGljaCBkaWZmZXJzIGZyb20g eW91ciBkcml2ZXIgaW4gdGhhdCB0aGUgUENJZSBQSFkgaXMNCj4gPiA+ID4gPiA+IG5vdCBhYnN0 cmFjdGVkIHRvIGl0cyBvd24gZHJpdmVyIHNvIEkgdGhpbmsgdGhpcyBoYXMgc29tZXRoaW5nDQo+ ID4gPiA+ID4gPiB0byBkbyB3aXRoIHRoZSBvcmRlciBpbiB3aGljaCB0aGUgcGh5IGlzIHJlc2V0 IG9yIGluaXRpYWxpemVkPw0KPiA+ID4gPiA+ID4gVGhlIGNvbmZpZ3VyYXRpb24gb2YNCj4gPiA+ ID4gZ3ByMTQgYml0cyBsb29rcyBjb3JyZWN0IHRvIG1lLg0KPiA+ID4gPiA+IFtSaWNoYXJkIFpo dV0gVGhlIENMS1JFUSMgUElOIGRlZmluaXRpb24gc2hvdWxkbid0IGJlIG1hc2tlZC4NCj4gPiA+ ID4gPiBJbiB0aGUgTlhQJ3MgbG9jYWwgQlNQIGtlcm5lbCwgSSBqdXN0IGZvcmNlIENMS1JFUSMg bG93IHRvIGxldmVsDQo+ID4gPiA+ID4gdXAgdGhlIEhXDQo+ID4gPiA+IGNvbXBhdGliaWxpdHku DQo+ID4gPiA+ID4gVGhhdCdzIG1pZ2h0IHRoZSByZWFzb24gd2h5IHRoZSBQQ0llIHdvcmtzIG9u IHlvdXIgSFcgYm9hcmQNCj4gPiA+ID4gPiBhbHRob3VnaCB0aGUNCj4gPiA+ID4gQ0xLUkVRIyBQ SU4gaXMgbm90IGRlZmluZWQuDQo+ID4gPiA+ID4gVGhpcyBtZXRob2QgaXMgYSBsaXR0bGUgcnVk ZSBhbmQgdmlvbGF0ZSB0aGUgU1BFQywgYW5kIG5vdA0KPiA+ID4gPiA+IHJlY29tbWVuZGVkDQo+ ID4gPiA+IGFsdGhvdWdoIGl0IGxldmVscyB1cCB0aGUgSFcgY29tcGF0aWJpbGl0eS4NCj4gPiA+ ID4gPiBTbyBJIGRyb3AgdGhpcyBtZXRob2QgaW4gdGhpcyBzZXJpZXMuDQo+ID4gPiA+ID4NCj4g PiA+ID4NCj4gPiA+ID4gU29ycnksIEkgZG9uJ3QgdW5kZXJzdGFuZCB3aGF0IHlvdSBhcmUgc2F5 aW5nIGhlcmUuIElzIHRoZXJlIGENCj4gPiA+ID4gY2hhbmdlIHlvdSBhcmUgZ29pbmcgdG8gbWFr ZSB0byB2NCB0aGF0IHdpbGwgbWFrZSB0aGlzIHdvcmsgZm9yDQo+ID4gPiA+IHRoZSBldmsgYW5k IG15IGJvYXJkcz8gV2hhdCBpcyB0aGF0IGNoYW5nZSBleGFjdGx5Pw0KPiA+ID4gW1JpY2hhcmQg Wmh1XSBOby4gV2hhdCBJIHNhaWQgYWJvdmUgaXMgdGhhdCB0aGUgQ0xLUkVRIyBpcyBmb3JjZWQg dG8NCj4gPiA+IGJlIGxvdyBpbiBOWFAgbG9jYWwgQlNQIGtlcm5lbC4gSSBndWVzcyB0aGlzIG1p Z2h0IGJlIHRoZSByZWFzb24gd2h5IHlvdXINCj4gYm9hcmQgd29ya3MuDQo+ID4gPg0KPiA+ID4g QklUMTEgYW5kIEJJVDEwIG9mIElPTVVYQ19HUFIxNCBjYW4gYmUgdXNlZCB0byBmb3JjZSB0aGUg Q0xLUkVRIyB0bw0KPiBiZSBsb3cuDQo+ID4gPiBTZXQgQ0xLUkVRX09WRVJSSURFX0VOKGJpdDEw KSAxYjEsIHRoZW4gd3JpdGUgb25lIHplcm8gdG8NCj4gQ0xLUkVRX09WRVJSSURFKGJpdDExKS4N Cj4gPiA+DQo+ID4NCj4gPiBPaywgdGhhdCBtYWtlcyBzZW5zZS4gVGhvc2UgYml0cyBhcmUgbm90 IGV4cGxhaW5lZCB3ZWxsIGluIHRoZQ0KPiA+IElNWDhNTVJNLiBBcyBteSBib2FyZCdzIGV4dGVy bmFsIFJFRkNMSyBpcyBhbHdheXMgZW5hYmxlZCB0aGF0IG11c3QNCj4gPiBnYXRlIHRoZSBjbG9j ayBpbnRlcm5hbGx5IHRvIHRoZSBob3N0IGNvbnRyb2xsZXIgYmxvY2suDQo+ID4NCj4gPiBJIGNh biBjb25maXJtIHRoYXQgYXNzZXJ0aW5nIHRob3NlIEdQUjE0IGJpdHMgZG9lcyByZXNvbHZlIG15 IGlzc3VlOg0KPiA+DQo+ID4gI2RlZmluZSBJTVg4TU1fR1BSX1BDSUVfQ0xLUkVRX09WRVJSSURF X1ZBTCAgICBCSVQoMTEpDQo+ID4gI2RlZmluZSBJTVg4TU1fR1BSX1BDSUVfQ0xLUkVRX09WRVJS SURFX0VOICAgICBCSVQoMTApDQo+ID4NCj4gPiAgICAgICAgLyoNCj4gPiAgICAgICAgICogZm9y IGJvYXJkcyB0aGF0IGRvIG5vdCBjb25uZWN0IENMS1JFUSMsDQo+ID4gICAgICAgICAqIG92ZXJy aWRlIENMS1JFUSMgYW5kIGRyaXZlIGl0IGxvdyBpbnRlcm5hbGx5DQo+ID4gICAgICAgICAqLw0K PiA+ICAgICAgICByZWdtYXBfdXBkYXRlX2JpdHMoaW14OF9waHktPmlvbXV4Y19ncHIsIElPTVVY Q19HUFIxNCwNCj4gPg0KPiBJTVg4TU1fR1BSX1BDSUVfQ0xLUkVRX09WRVJSSURFX1ZBTCwgMCk7 DQo+ID4gICAgICAgIHJlZ21hcF91cGRhdGVfYml0cyhpbXg4X3BoeS0+aW9tdXhjX2dwciwgSU9N VVhDX0dQUjE0LA0KPiA+DQo+IElNWDhNTV9HUFJfUENJRV9DTEtSRVFfT1ZFUlJJREVfRU4sIDEp Ow0KW1JpY2hhcmQgWmh1XSByZWdtYXAgYml0cyBvcGVyYXRpb25zIHNob3VsZCBtYW5pcHVsYXRl IGFjY29yZGluZyBiaXRzLg0KVGhlIEJJVCgxMCkgYW5kIEJJVCgxMSkgc2hvdWxkIGJlIHRvdWNo ZWQgYWN0dWFsbHkuDQoNCj4gPg0KPiA+IFNob3VsZCB0aGlzIGJlIGFkZGVkIGFzIGEgJ2ZzbCxj bGtyZXEtdW5zdXBwb3J0ZWQnIGZsYWcgdGhhdCBuZWVkcyB0bw0KPiA+IGJlIHNldCB0cnVlIHRv IGltcGxlbWVudCB0aGUgYWJvdmUgY29kZT8NCj4gPg0KPiANCj4gUmljaGFyZCwNCj4gDQo+IFNv cnJ5IC0gc3Bva2UgdG9vIHNvb24uIE15IHRlc3Qgd2FzIGZsYXdlZCBhcyBJIHN0aWxsIHdhcyBw aW5tdXhpbmcgQ0xLUkVRIGluDQo+IG15IGR0IHRvIHdvcmsgYXJvdW5kIHRoZSBpc3N1ZSBhbmQg YWZ0ZXIgcmVtb3ZlZCB0aGUgYWJvdmUgZGlkIG5vdCByZXNvbHZlDQo+IG15IGlzc3VlLiBUaGUg c2V0dGluZyBvZiBPVkVSUklERV9FTiB3YXMgd3JvbmcgYWJvdmUgKHNob3VsZCBub3QgYmUgc2V0 IHRvDQo+ICcxJyBidXQgQklUKDEwKSBpbnN0ZWFkKSBidXQgdGhpcyBjb2RlIGFscmVhZHkgZXhp c3RzIGluDQo+IGlteDZfcGNpZV9lbmFibGVfcmVmX2NsayBhbmQgaXMgdXNlZCBmb3IgSU1YOE1N IHBlciB5b3VyIHBhdGNoIHNvIHRoaXMgaXMNCj4gbm90IHRoZSBpc3N1ZS4NCj4gDQo+IFdoYXQg bWFrZXMgbXkgYm9hcmQgd29yayBpcyB0byBjbGVhciBHUFIxNCBiaXQ5IChsaWtlIHRoZSBOWFAg a2VybmVsDQo+IGRvZXMpIHNvIEkgZG9uJ3QgdGhpbmsgdGhpcyBiaXQgZG9lcyB3aGF0IHdlIHRo aW5rIGl0IGRvZXMgKHNlbGVjdCBiZXR3ZWVuDQo+IGludGVybmFsIGFuZCBleHQgY2xrKS4gSSB0 aGluayBzZXR0aW5nIGl0IGVuYWJsZXMgY2xvY2sgZ2F0aW5nIHZpYSBDTEtSRVEjLg0KPiANCj4g VGhpcyBhbHNvIHBvaW50cyBvdXQgdGhhdCBwZXJoYXBzIHRoZSBDTEtSRVFfT1ZFUlJJREUgbG9n aWMgc2hvdWxkIGJlDQo+IG1vdmVkIHRvIHRoZSBuZXcgcGh5IGRyaXZlciBmb3IgSU1YOE1NLg0K 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=?utf-8?B?Tm5qNzFEYzh1UEFYbnQzQjVHUFF4YlZRL1NUcDc3Qk9sTHU0SThlRWRiNlAv?= =?utf-8?B?bU8yZHFtbzVvaStiVG9RWTVVME53V1IxYVZGZTZwczdqbDdZb3lyV1RJc04x?= =?utf-8?B?RVR4d0UwYmlwQ1hSemFuZGhqcE1pUWlTZ1JQS3FQVEhSajM5VkdVNGgvNGZw?= =?utf-8?B?UGtDUGdseXVkTDRadi9SaUpnZmhKZE5WeTRnZm9SbGd5eGd5QmdIc2xzV2tL?= =?utf-8?B?aGIzTXlEc3ZPNWppMWtrb2J1cDVvNTh6amt4V2NzbnY3RVJMYjlPWkYxUGlG?= =?utf-8?B?MGd6REJEV1QzNkh6Z0xncmFMWGxJTVFqOTAvNCtCc2pnSk1vSVR3akludzR3?= =?utf-8?B?UGFvbG9ISXV3V1NXL2NzWVVKcmNOMlFLa2VsamN6Nnoxa25pZytYSlFTYTlT?= =?utf-8?B?M2lsMU9GeVRCb1V0eVdrbHRLNXpXeHRrY0dCdEppY3hVYmhGZkNrSFhkK0pV?= =?utf-8?B?UWd1SFhFL1lnbFJ5eTVNT0M4UTd4MWI3N0xkQ28vMUhra2VlbEJSeXNFSEEr?= =?utf-8?B?ODZKdzcxbFo0ZnpYUW1jVHVnMG5rZDdnSDFwZys1MENMVWFORWg5VTZYOXdQ?= =?utf-8?B?WVl5SjFmSEo4OHBiNmVmNXZPYzdXcU15SU85cEdjMnA2U3krdGo5bXhHWWE2?= =?utf-8?B?dHNxRGNZUGVlbWlIQTllQXRRQWYxS1hXV3NxODM2Rkd2VDlaZjRHU05RNmFS?= =?utf-8?B?ZnJNdVMvVEx2NW5TL09odHg2dFl6VE5icTI3dDVxbUU3MnZrNHFGdlQyQTFQ?= =?utf-8?B?SkZBc0haSTFhMGtRYlFJbCtRSEhkaXRpUU1UR2Q1RVdZeW9BL2MrZWF6bHIv?= =?utf-8?B?YTd6SzJ3U1BrNVh2b0ovSktHV2ZFeGJ4T2tyUG95TEpKNE13dHhqS1NHdXl5?= =?utf-8?B?RmpNNThDWm9QVXBIVlYybGtpSENjOHcyZEpzZTVDNU9rUC9kdjNuTU55RSts?= =?utf-8?B?dzM5K3I1LzUxeWxXV2RDTjd6dmhFQXM4WitoQkZwUHNTVFlVQmkrUTJpTDhx?= =?utf-8?B?elNLY3NKV3RvcGhjT2lmMXZVdHYyU3JmRjRBZ0Y3UmpRR21RZ0pkZ25UUkNq?= =?utf-8?B?VGVUNnU5SzRxMTVMZm5OWWU3Z0QvZmNOejN1WDh3dlNWc0Q2UTFOQmZObStW?= =?utf-8?B?bHp2RGdnOXM2RFlYejQ0Tytra051dGhkd09hQXZOU093TVFJOFFiUzBTcm45?= =?utf-8?B?TGI3U2R0S1IvUFhBanNDejVqMXc2NTZoNTFwbkZqbmRuYkNqUDdmbmJhWWFT?= =?utf-8?B?MkkyUklOZTdiUzlKS1BnanIwNWRJeDUyY2ROcXg0SzZCQmIxUms0QzFVWFli?= =?utf-8?B?UlkwN2JhRlE1cFZQSUhHWEUrV1ZaK0g1bm5oTEM1TG1CMG8zYWVQYkR6ODlm?= =?utf-8?B?UkdlK09KWURWaGpoSzlhQjRCWXkrUHE4aGhheWUzQ2RUbzQ4STFMU094YlZM?= =?utf-8?B?elk5RjVoMk9USTZVSnlzQU9FOFRIRWdMeHkzaisvU2kzMGNpZXJkS0x0d25o?= =?utf-8?B?SjRiRlQzZGRocldQY3hWSlBwZU5aZG5kT2hyZ1RPekpGZytHdW1QcEVlWXhn?= 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MR-646709E3 X-CRM114-CacheID: sfid-20211024_191305_375437_A6E6C38B X-CRM114-Status: GOOD ( 36.44 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org > -----Original Message----- > From: Tim Harvey > Sent: Saturday, October 23, 2021 12:55 AM > To: Richard Zhu > Cc: Lucas Stach ; Kishon Vijay Abraham I > ; vkoul@kernel.org; Rob Herring ; > galak@kernel.crashing.org; Shawn Guo ; > linux-phy@lists.infradead.org; Device Tree Mailing List > ; Linux ARM Mailing List > ; open list > ; Sascha Hauer ; > dl-linux-imx > Subject: Re: [PATCH v3 0/9] add the imx8m pcie phy driver and imx8mm pcie > support > > On Fri, Oct 22, 2021 at 8:59 AM Tim Harvey > wrote: > > > > On Thu, Oct 21, 2021 at 5:43 PM Richard Zhu > wrote: > > > > > > > -----Original Message----- > > > > From: Tim Harvey > > > > Sent: Friday, October 22, 2021 12:25 AM > > > > To: Richard Zhu > > > > Cc: Lucas Stach ; Kishon Vijay Abraham I > > > > ; vkoul@kernel.org; Rob Herring ; > > > > galak@kernel.crashing.org; Shawn Guo ; > > > > linux-phy@lists.infradead.org; Device Tree Mailing List > > > > ; Linux ARM Mailing List > > > > ; open list > > > > ; Sascha Hauer > > > > ; dl-linux-imx > > > > Subject: Re: [PATCH v3 0/9] add the imx8m pcie phy driver and > > > > imx8mm pcie support > > > > > > > > On Wed, Oct 20, 2021 at 8:32 PM Richard Zhu > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > Richard, > > > > > > > > > > > > What is this 'invalid resource' about? I see that with my > > > > > > downstream IMX8MM PCIe driver as well and have been asked > about it. > > > > > > > > > > > [Richard Zhu] Hi Tim: > > > > > This complain is caused by the following codes in pcie-designware.c > driver. > > > > > I'm not sure that why there is only size assignment after the > > > > > res valid check, > > > > and do nothing if the res is invalid. > > > > > It seems that it is an expected design logic refer to the later codes. > > > > > if (!pci->atu_base) { > > > > > struct resource *res = > > > > > > > > > platform_get_resource_byname(pdev, IORESOURCE_MEM, "atu"); > > > > > if (res) > > > > > pci->atu_size = > resource_size(res); > > > > > pci->atu_base = > > > > devm_ioremap_resource(dev, res); > > > > > if (IS_ERR(pci->atu_base)) > > > > > pci->atu_base = > pci->dbi_base + > > > > DEFAULT_DBI_ATU_OFFSET; > > > > > } > > > > > > > > > > Since the default offset is used on i.MX8MM, the "atu" is not > > > > > specified in > > > > i.MX8MM PCIe DT node, so there is no real res at all. > > > > > Then, devm_ioremap_resource() would complain the invalid resource. > > > > > > > > I think you are saying a change should be made like this: > > > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c > > > > b/drivers/pci/controller/dwc/pcie-designware.c > > > > index a945f0c0e73d..3254f60d1713 100644 > > > > --- a/drivers/pci/controller/dwc/pcie-designware.c > > > > +++ b/drivers/pci/controller/dwc/pcie-designware.c > > > > @@ -671,10 +671,11 @@ void dw_pcie_iatu_detect(struct dw_pcie > *pci) > > > > if (!pci->atu_base) { > > > > struct resource *res = > > > > > > > > platform_get_resource_byname(pdev, > > > > IORESOURCE_MEM, "atu"); > > > > - if (res) > > > > + if (res) { > > > > pci->atu_size = > resource_size(res); > > > > - pci->atu_base = > devm_ioremap_resource(dev, > > > > res); > > > > - if (IS_ERR(pci->atu_base)) > > > > + pci->atu_base = > > > > devm_ioremap_resource(dev, res); > > > > + } > > > > + if (!pci->atu_base || > > > > + IS_ERR(pci->atu_base)) > > > > pci->atu_base = pci->dbi_base > + > > > > DEFAULT_DBI_ATU_OFFSET; > > > > } > > > > > > > > so that it looks like this: > > > > if (!pci->atu_base) { > > > > struct resource *res = > > > > > > > > platform_get_resource_byname(pdev, > > > > IORESOURCE_MEM, "atu"); > > > > if (res) { > > > > pci->atu_size = > resource_size(res); > > > > pci->atu_base = > > > > devm_ioremap_resource(dev, res); > > > > } > > > > if (!pci->atu_base || > IS_ERR(pci->atu_base)) > > > > pci->atu_base = pci->dbi_base > + > > > > DEFAULT_DBI_ATU_OFFSET; > > > > } > > > > > > > > Right? > > > [Richard Zhu] Yes, it is. The res shouldn't be remapped if it is invalid > resource memory. > > > > Ok, I will submit a patch for that. > > [Richard Zhu] Thanks for your help. Please cc me, if you issue that patch. > > > > > > > > > > > > > > > > > > > [ 1.316305] imx6q-pcie 33800000.pcie: iATU unroll: enabled > > > > > > > [ 1.321799] imx6q-pcie 33800000.pcie: Detected iATU regions: > 4 > > > > > > outbound, 4 inbound > > > > > > > [ 1.429803] imx6q-pcie 33800000.pcie: Link up > > > > > > > [ 1.534497] imx6q-pcie 33800000.pcie: Link up > > > > > > > [ 1.538870] imx6q-pcie 33800000.pcie: Link up, Gen2 > > > > > > > [ 1.550364] imx6q-pcie 33800000.pcie: Link up > > > > > > > [ 1.550487] imx6q-pcie 33800000.pcie: PCI host bridge to bus > > > > 0000:00 > > > > > > > [ 1.565545] pci_bus 0000:00: root bus resource [bus 00-ff] > > > > > > > [ 1.573834] pci_bus 0000:00: root bus resource [io > 0x0000-0xffff] > > > > > > > [ 1.580055] pci_bus 0000:00: root bus resource [mem > > > > > > 0x18000000-0x1fefffff] > > > > > > > [ 1.586968] pci 0000:00:00.0: [16c3:abcd] type 01 class > 0x060400 > > > > > > > [ 1.592997] pci 0000:00:00.0: reg 0x10: [mem > > > > 0x00000000-0x000fffff] > > > > > > > [ 1.599282] pci 0000:00:00.0: reg 0x38: [mem > > > > 0x00000000-0x0000ffff > > > > > > pref] > > > > > > > [ 1.606033] pci 0000:00:00.0: supports D1 > > > > > > > [ 1.610053] pci 0000:00:00.0: PME# supported from D0 D1 > D3hot > > > > > > D3cold > > > > > > > [ 1.618206] pci 0000:01:00.0: [15b7:5002] type 00 class > 0x010802 > > > > > > > [ 1.624293] pci 0000:01:00.0: reg 0x10: [mem > > > > 0x00000000-0x00003fff > > > > > > 64bit] > > > > > > > [ 1.631177] pci 0000:01:00.0: reg 0x20: [mem > > > > 0x00000000-0x000000ff > > > > > > 64bit] > > > > > > > [ 1.638409] pci 0000:01:00.0: 4.000 Gb/s available PCIe > bandwidth, > > > > > > limited by 5.0 GT/s PCIe x1 link at 0000:00:00.0 (capable of > > > > > > 31.504 Gb/s with > > > > > > 8.0 GT/s PCIe x4 link) > > > > > > > [ 1.664931] pci 0000:00:00.0: BAR 0: assigned [mem > > > > > > 0x18000000-0x180fffff] > > > > > > > [ 1.671745] pci 0000:00:00.0: BAR 14: assigned [mem > > > > > > 0x18100000-0x181fffff] > > > > > > > [ 1.678634] pci 0000:00:00.0: BAR 6: assigned [mem > > > > > > 0x18200000-0x1820ffff pref] > > > > > > > [ 1.685873] pci 0000:01:00.0: BAR 0: assigned [mem > > > > > > 0x18100000-0x18103fff 64bit] > > > > > > > [ 1.693222] pci 0000:01:00.0: BAR 4: assigned [mem > > > > > > 0x18104000-0x181040ff 64bit] > > > > > > > [ 1.700577] pci 0000:00:00.0: PCI bridge to [bus 01-ff] > > > > > > > [ 1.705814] pci 0000:00:00.0: bridge window [mem > > > > > > 0x18100000-0x181fffff] > > > > > > > [ 1.712972] pcieport 0000:00:00.0: PME: Signaling with IRQ > 216 > > > > > > > " > > > > > > > Regarding the log you pasted, it seems that the clock is not > > > > > > > feed to PHY > > > > > > properly. > > > > > > > > > > > > > > Anyway, let's waiting for the v4 series, then make a try. > > > > > > > Thanks for your > > > > > > great help to make the double tests. > > > > > > > > > > > > > > > > > > > My boards do not use CLKREQ# so I do not have that defined in > > > > > > pinmux and I found that if I add > > > > > > MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B > > > > PCIe > > > > > > works on my board but this isn't a solution just a work-around > > > > > > (I have boards that use the only two possible pins for CLKREQ > > > > > > as other > > > > features). > > > > > > > > > > > > Similarly you will find on the imx8mm-evk if you comment out > > > > > > the CLKREQ (which isn't required) the imx8mmevk will end up > > > > > > hanging like my > > > > boards: > > > > > [Richard Zhu] Hi Tim: > > > > > Regarding the SPEC, the CLKREQ# is mandatory required, and > > > > > should be > > > > configured as an open drain, active low signal. > > > > > And this signal should be driven low by the PCIe M.2 device to > > > > > request the > > > > REF clock be available(active low). > > > > > So, there is such kind of CLKREQ# pin definition on i.MX8MM EVK > board. > > > > > > > > > > Anyway, I think the external OSC circuit should be always > > > > > running if there is > > > > no CLKREQ# on your HW board design. > > > > > > > > > > > > > The way I understand it is CLKREQ# allows the host to disable the > > > > REFCLK when not needed for power savings so it would seem optional > > > > to implement that and if not implemented should be left unconnected on > the card. > > > > > > > [Richard Zhu] No, not that way. Regarding the SPEC, this signal is > mandatory required. > > > Especially for the L1ss usages. This signal would be OD(open drain), > > > bi-directional, and might be driven low/high by RC or EP automatically if > L1ss modes are enabled. > > > You can make reference to the > > > "ECN_L1_PM_Substates_with_CLKREQ_31_May_2013_Rev10a", or the > chapter 5.5 L1 PM Substates of "PCI Express Base Specification, Rev. 4.0 > Version 1.0". > > > > > > > CLKREQ is only mandatory if you wish to support clock power > > management. Many boards with a PCI host controller do not support > > this. [Richard Zhu] Okay, understood. > > > > > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi > > > > > > b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi > > > > > > index 5ce43daa0c8b..f0023b48f475 100644 > > > > > > --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi > > > > > > +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi > > > > > > @@ -448,7 +448,9 @@ > > > > > > > > > > > > pinctrl_pcie0: pcie0grp { > > > > > > fsl,pins = < > > > > > > +/* > > > > > > > > > > > > MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61 > > > > > > +*/ > > > > > > > > > > MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 > > > > > > 0x41 > > > > > > >; > > > > > > }; > > > > > > > > > > > > I have PCIe working with a driver that I ported from NXP's > > > > > > kernel which differs from your driver in that the PCIe PHY is > > > > > > not abstracted to its own driver so I think this has something > > > > > > to do with the order in which the phy is reset or initialized? > > > > > > The configuration of > > > > gpr14 bits looks correct to me. > > > > > [Richard Zhu] The CLKREQ# PIN definition shouldn't be masked. > > > > > In the NXP's local BSP kernel, I just force CLKREQ# low to level > > > > > up the HW > > > > compatibility. > > > > > That's might the reason why the PCIe works on your HW board > > > > > although the > > > > CLKREQ# PIN is not defined. > > > > > This method is a little rude and violate the SPEC, and not > > > > > recommended > > > > although it levels up the HW compatibility. > > > > > So I drop this method in this series. > > > > > > > > > > > > > Sorry, I don't understand what you are saying here. Is there a > > > > change you are going to make to v4 that will make this work for > > > > the evk and my boards? What is that change exactly? > > > [Richard Zhu] No. What I said above is that the CLKREQ# is forced to > > > be low in NXP local BSP kernel. I guess this might be the reason why your > board works. > > > > > > BIT11 and BIT10 of IOMUXC_GPR14 can be used to force the CLKREQ# to > be low. > > > Set CLKREQ_OVERRIDE_EN(bit10) 1b1, then write one zero to > CLKREQ_OVERRIDE(bit11). > > > > > > > Ok, that makes sense. Those bits are not explained well in the > > IMX8MMRM. As my board's external REFCLK is always enabled that must > > gate the clock internally to the host controller block. > > > > I can confirm that asserting those GPR14 bits does resolve my issue: > > > > #define IMX8MM_GPR_PCIE_CLKREQ_OVERRIDE_VAL BIT(11) > > #define IMX8MM_GPR_PCIE_CLKREQ_OVERRIDE_EN BIT(10) > > > > /* > > * for boards that do not connect CLKREQ#, > > * override CLKREQ# and drive it low internally > > */ > > regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, > > > IMX8MM_GPR_PCIE_CLKREQ_OVERRIDE_VAL, 0); > > regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, > > > IMX8MM_GPR_PCIE_CLKREQ_OVERRIDE_EN, 1); [Richard Zhu] regmap bits operations should manipulate according bits. The BIT(10) and BIT(11) should be touched actually. > > > > Should this be added as a 'fsl,clkreq-unsupported' flag that needs to > > be set true to implement the above code? > > > > Richard, > > Sorry - spoke too soon. My test was flawed as I still was pinmuxing CLKREQ in > my dt to work around the issue and after removed the above did not resolve > my issue. The setting of OVERRIDE_EN was wrong above (should not be set to > '1' but BIT(10) instead) but this code already exists in > imx6_pcie_enable_ref_clk and is used for IMX8MM per your patch so this is > not the issue. > > What makes my board work is to clear GPR14 bit9 (like the NXP kernel > does) so I don't think this bit does what we think it does (select between > internal and ext clk). I think setting it enables clock gating via CLKREQ#. > > This also points out that perhaps the CLKREQ_OVERRIDE logic should be > moved to the new phy driver for IMX8MM. [Richard Zhu] It sounds reasonable to consider to force the CLKREQ# to be low. I will think about that and add this in later v5 patch-set if nobody has different concerns. Thanks. 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org > -----Original Message----- > From: Tim Harvey > Sent: Saturday, October 23, 2021 12:55 AM > To: Richard Zhu > Cc: Lucas Stach ; Kishon Vijay Abraham I > ; vkoul@kernel.org; Rob Herring ; > galak@kernel.crashing.org; Shawn Guo ; > linux-phy@lists.infradead.org; Device Tree Mailing List > ; Linux ARM Mailing List > ; open list > ; Sascha Hauer ; > dl-linux-imx > Subject: Re: [PATCH v3 0/9] add the imx8m pcie phy driver and imx8mm pcie > support > > On Fri, Oct 22, 2021 at 8:59 AM Tim Harvey > wrote: > > > > On Thu, Oct 21, 2021 at 5:43 PM Richard Zhu > wrote: > > > > > > > -----Original Message----- > > > > From: Tim Harvey > > > > Sent: Friday, October 22, 2021 12:25 AM > > > > To: Richard Zhu > > > > Cc: Lucas Stach ; Kishon Vijay Abraham I > > > > ; vkoul@kernel.org; Rob Herring ; > > > > galak@kernel.crashing.org; Shawn Guo ; > > > > linux-phy@lists.infradead.org; Device Tree Mailing List > > > > ; Linux ARM Mailing List > > > > ; open list > > > > ; Sascha Hauer > > > > ; dl-linux-imx > > > > Subject: Re: [PATCH v3 0/9] add the imx8m pcie phy driver and > > > > imx8mm pcie support > > > > > > > > On Wed, Oct 20, 2021 at 8:32 PM Richard Zhu > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > Richard, > > > > > > > > > > > > What is this 'invalid resource' about? I see that with my > > > > > > downstream IMX8MM PCIe driver as well and have been asked > about it. > > > > > > > > > > > [Richard Zhu] Hi Tim: > > > > > This complain is caused by the following codes in pcie-designware.c > driver. > > > > > I'm not sure that why there is only size assignment after the > > > > > res valid check, > > > > and do nothing if the res is invalid. > > > > > It seems that it is an expected design logic refer to the later codes. > > > > > if (!pci->atu_base) { > > > > > struct resource *res = > > > > > > > > > platform_get_resource_byname(pdev, IORESOURCE_MEM, "atu"); > > > > > if (res) > > > > > pci->atu_size = > resource_size(res); > > > > > pci->atu_base = > > > > devm_ioremap_resource(dev, res); > > > > > if (IS_ERR(pci->atu_base)) > > > > > pci->atu_base = > pci->dbi_base + > > > > DEFAULT_DBI_ATU_OFFSET; > > > > > } > > > > > > > > > > Since the default offset is used on i.MX8MM, the "atu" is not > > > > > specified in > > > > i.MX8MM PCIe DT node, so there is no real res at all. > > > > > Then, devm_ioremap_resource() would complain the invalid resource. > > > > > > > > I think you are saying a change should be made like this: > > > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c > > > > b/drivers/pci/controller/dwc/pcie-designware.c > > > > index a945f0c0e73d..3254f60d1713 100644 > > > > --- a/drivers/pci/controller/dwc/pcie-designware.c > > > > +++ b/drivers/pci/controller/dwc/pcie-designware.c > > > > @@ -671,10 +671,11 @@ void dw_pcie_iatu_detect(struct dw_pcie > *pci) > > > > if (!pci->atu_base) { > > > > struct resource *res = > > > > > > > > platform_get_resource_byname(pdev, > > > > IORESOURCE_MEM, "atu"); > > > > - if (res) > > > > + if (res) { > > > > pci->atu_size = > resource_size(res); > > > > - pci->atu_base = > devm_ioremap_resource(dev, > > > > res); > > > > - if (IS_ERR(pci->atu_base)) > > > > + pci->atu_base = > > > > devm_ioremap_resource(dev, res); > > > > + } > > > > + if (!pci->atu_base || > > > > + IS_ERR(pci->atu_base)) > > > > pci->atu_base = pci->dbi_base > + > > > > DEFAULT_DBI_ATU_OFFSET; > > > > } > > > > > > > > so that it looks like this: > > > > if (!pci->atu_base) { > > > > struct resource *res = > > > > > > > > platform_get_resource_byname(pdev, > > > > IORESOURCE_MEM, "atu"); > > > > if (res) { > > > > pci->atu_size = > resource_size(res); > > > > pci->atu_base = > > > > devm_ioremap_resource(dev, res); > > > > } > > > > if (!pci->atu_base || > IS_ERR(pci->atu_base)) > > > > pci->atu_base = pci->dbi_base > + > > > > DEFAULT_DBI_ATU_OFFSET; > > > > } > > > > > > > > Right? > > > [Richard Zhu] Yes, it is. The res shouldn't be remapped if it is invalid > resource memory. > > > > Ok, I will submit a patch for that. > > [Richard Zhu] Thanks for your help. Please cc me, if you issue that patch. > > > > > > > > > > > > > > > > > > > [ 1.316305] imx6q-pcie 33800000.pcie: iATU unroll: enabled > > > > > > > [ 1.321799] imx6q-pcie 33800000.pcie: Detected iATU regions: > 4 > > > > > > outbound, 4 inbound > > > > > > > [ 1.429803] imx6q-pcie 33800000.pcie: Link up > > > > > > > [ 1.534497] imx6q-pcie 33800000.pcie: Link up > > > > > > > [ 1.538870] imx6q-pcie 33800000.pcie: Link up, Gen2 > > > > > > > [ 1.550364] imx6q-pcie 33800000.pcie: Link up > > > > > > > [ 1.550487] imx6q-pcie 33800000.pcie: PCI host bridge to bus > > > > 0000:00 > > > > > > > [ 1.565545] pci_bus 0000:00: root bus resource [bus 00-ff] > > > > > > > [ 1.573834] pci_bus 0000:00: root bus resource [io > 0x0000-0xffff] > > > > > > > [ 1.580055] pci_bus 0000:00: root bus resource [mem > > > > > > 0x18000000-0x1fefffff] > > > > > > > [ 1.586968] pci 0000:00:00.0: [16c3:abcd] type 01 class > 0x060400 > > > > > > > [ 1.592997] pci 0000:00:00.0: reg 0x10: [mem > > > > 0x00000000-0x000fffff] > > > > > > > [ 1.599282] pci 0000:00:00.0: reg 0x38: [mem > > > > 0x00000000-0x0000ffff > > > > > > pref] > > > > > > > [ 1.606033] pci 0000:00:00.0: supports D1 > > > > > > > [ 1.610053] pci 0000:00:00.0: PME# supported from D0 D1 > D3hot > > > > > > D3cold > > > > > > > [ 1.618206] pci 0000:01:00.0: [15b7:5002] type 00 class > 0x010802 > > > > > > > [ 1.624293] pci 0000:01:00.0: reg 0x10: [mem > > > > 0x00000000-0x00003fff > > > > > > 64bit] > > > > > > > [ 1.631177] pci 0000:01:00.0: reg 0x20: [mem > > > > 0x00000000-0x000000ff > > > > > > 64bit] > > > > > > > [ 1.638409] pci 0000:01:00.0: 4.000 Gb/s available PCIe > bandwidth, > > > > > > limited by 5.0 GT/s PCIe x1 link at 0000:00:00.0 (capable of > > > > > > 31.504 Gb/s with > > > > > > 8.0 GT/s PCIe x4 link) > > > > > > > [ 1.664931] pci 0000:00:00.0: BAR 0: assigned [mem > > > > > > 0x18000000-0x180fffff] > > > > > > > [ 1.671745] pci 0000:00:00.0: BAR 14: assigned [mem > > > > > > 0x18100000-0x181fffff] > > > > > > > [ 1.678634] pci 0000:00:00.0: BAR 6: assigned [mem > > > > > > 0x18200000-0x1820ffff pref] > > > > > > > [ 1.685873] pci 0000:01:00.0: BAR 0: assigned [mem > > > > > > 0x18100000-0x18103fff 64bit] > > > > > > > [ 1.693222] pci 0000:01:00.0: BAR 4: assigned [mem > > > > > > 0x18104000-0x181040ff 64bit] > > > > > > > [ 1.700577] pci 0000:00:00.0: PCI bridge to [bus 01-ff] > > > > > > > [ 1.705814] pci 0000:00:00.0: bridge window [mem > > > > > > 0x18100000-0x181fffff] > > > > > > > [ 1.712972] pcieport 0000:00:00.0: PME: Signaling with IRQ > 216 > > > > > > > " > > > > > > > Regarding the log you pasted, it seems that the clock is not > > > > > > > feed to PHY > > > > > > properly. > > > > > > > > > > > > > > Anyway, let's waiting for the v4 series, then make a try. > > > > > > > Thanks for your > > > > > > great help to make the double tests. > > > > > > > > > > > > > > > > > > > My boards do not use CLKREQ# so I do not have that defined in > > > > > > pinmux and I found that if I add > > > > > > MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B > > > > PCIe > > > > > > works on my board but this isn't a solution just a work-around > > > > > > (I have boards that use the only two possible pins for CLKREQ > > > > > > as other > > > > features). > > > > > > > > > > > > Similarly you will find on the imx8mm-evk if you comment out > > > > > > the CLKREQ (which isn't required) the imx8mmevk will end up > > > > > > hanging like my > > > > boards: > > > > > [Richard Zhu] Hi Tim: > > > > > Regarding the SPEC, the CLKREQ# is mandatory required, and > > > > > should be > > > > configured as an open drain, active low signal. > > > > > And this signal should be driven low by the PCIe M.2 device to > > > > > request the > > > > REF clock be available(active low). > > > > > So, there is such kind of CLKREQ# pin definition on i.MX8MM EVK > board. > > > > > > > > > > Anyway, I think the external OSC circuit should be always > > > > > running if there is > > > > no CLKREQ# on your HW board design. > > > > > > > > > > > > > The way I understand it is CLKREQ# allows the host to disable the > > > > REFCLK when not needed for power savings so it would seem optional > > > > to implement that and if not implemented should be left unconnected on > the card. > > > > > > > [Richard Zhu] No, not that way. Regarding the SPEC, this signal is > mandatory required. > > > Especially for the L1ss usages. This signal would be OD(open drain), > > > bi-directional, and might be driven low/high by RC or EP automatically if > L1ss modes are enabled. > > > You can make reference to the > > > "ECN_L1_PM_Substates_with_CLKREQ_31_May_2013_Rev10a", or the > chapter 5.5 L1 PM Substates of "PCI Express Base Specification, Rev. 4.0 > Version 1.0". > > > > > > > CLKREQ is only mandatory if you wish to support clock power > > management. Many boards with a PCI host controller do not support > > this. [Richard Zhu] Okay, understood. > > > > > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi > > > > > > b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi > > > > > > index 5ce43daa0c8b..f0023b48f475 100644 > > > > > > --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi > > > > > > +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi > > > > > > @@ -448,7 +448,9 @@ > > > > > > > > > > > > pinctrl_pcie0: pcie0grp { > > > > > > fsl,pins = < > > > > > > +/* > > > > > > > > > > > > MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61 > > > > > > +*/ > > > > > > > > > > MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 > > > > > > 0x41 > > > > > > >; > > > > > > }; > > > > > > > > > > > > I have PCIe working with a driver that I ported from NXP's > > > > > > kernel which differs from your driver in that the PCIe PHY is > > > > > > not abstracted to its own driver so I think this has something > > > > > > to do with the order in which the phy is reset or initialized? > > > > > > The configuration of > > > > gpr14 bits looks correct to me. > > > > > [Richard Zhu] The CLKREQ# PIN definition shouldn't be masked. > > > > > In the NXP's local BSP kernel, I just force CLKREQ# low to level > > > > > up the HW > > > > compatibility. > > > > > That's might the reason why the PCIe works on your HW board > > > > > although the > > > > CLKREQ# PIN is not defined. > > > > > This method is a little rude and violate the SPEC, and not > > > > > recommended > > > > although it levels up the HW compatibility. > > > > > So I drop this method in this series. > > > > > > > > > > > > > Sorry, I don't understand what you are saying here. Is there a > > > > change you are going to make to v4 that will make this work for > > > > the evk and my boards? What is that change exactly? > > > [Richard Zhu] No. What I said above is that the CLKREQ# is forced to > > > be low in NXP local BSP kernel. I guess this might be the reason why your > board works. > > > > > > BIT11 and BIT10 of IOMUXC_GPR14 can be used to force the CLKREQ# to > be low. > > > Set CLKREQ_OVERRIDE_EN(bit10) 1b1, then write one zero to > CLKREQ_OVERRIDE(bit11). > > > > > > > Ok, that makes sense. Those bits are not explained well in the > > IMX8MMRM. As my board's external REFCLK is always enabled that must > > gate the clock internally to the host controller block. > > > > I can confirm that asserting those GPR14 bits does resolve my issue: > > > > #define IMX8MM_GPR_PCIE_CLKREQ_OVERRIDE_VAL BIT(11) > > #define IMX8MM_GPR_PCIE_CLKREQ_OVERRIDE_EN BIT(10) > > > > /* > > * for boards that do not connect CLKREQ#, > > * override CLKREQ# and drive it low internally > > */ > > regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, > > > IMX8MM_GPR_PCIE_CLKREQ_OVERRIDE_VAL, 0); > > regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, > > > IMX8MM_GPR_PCIE_CLKREQ_OVERRIDE_EN, 1); [Richard Zhu] regmap bits operations should manipulate according bits. The BIT(10) and BIT(11) should be touched actually. > > > > Should this be added as a 'fsl,clkreq-unsupported' flag that needs to > > be set true to implement the above code? > > > > Richard, > > Sorry - spoke too soon. My test was flawed as I still was pinmuxing CLKREQ in > my dt to work around the issue and after removed the above did not resolve > my issue. The setting of OVERRIDE_EN was wrong above (should not be set to > '1' but BIT(10) instead) but this code already exists in > imx6_pcie_enable_ref_clk and is used for IMX8MM per your patch so this is > not the issue. > > What makes my board work is to clear GPR14 bit9 (like the NXP kernel > does) so I don't think this bit does what we think it does (select between > internal and ext clk). I think setting it enables clock gating via CLKREQ#. > > This also points out that perhaps the CLKREQ_OVERRIDE logic should be > moved to the new phy driver for IMX8MM. [Richard Zhu] It sounds reasonable to consider to force the CLKREQ# to be low. I will think about that and add this in later v5 patch-set if nobody has different concerns. Thanks. BR Richard > > Best regards, > > Tim _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel