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From: Stephane Eranian <eranian@google.com>
To: Robert Richter <robert.richter@amd.com>
Cc: Peter Zijlstra <peterz@infradead.org>,
	Ingo Molnar <mingo@elte.hu>, LKML <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 4/4] perf, x86: Fix event scheduler to solve complex scheduling problems
Date: Sun, 17 Apr 2011 02:05:47 -0700	[thread overview]
Message-ID: <BANLkTik-NNny1TQroMmLKpZA-q8HshXBUg@mail.gmail.com> (raw)
In-Reply-To: <20110417084432.GM31407@erda.amd.com>

On Sun, Apr 17, 2011 at 1:44 AM, Robert Richter <robert.richter@amd.com> wrote:
> On 16.04.11 11:52:54, Stephane Eranian wrote:
>> On Fri, Apr 15, 2011 at 5:27 PM, Robert Richter <robert.richter@amd.com> wrote:
>
>> >        event code      counter         failure         possible solution
>> >
>> > 1)      0x043           PMC[2:0]        0               1
>> >        0x02E           PMC[3,0]        3               0
>> >        0x003           PMC3            FAIL            3
>> >
>> I am not sure I understand this failure case. If I recall
>> the scheduler looks at the weight of each event first:
>>
>>                                             weight
>> 1)      0x043           PMC[2:0]  3
>>         0x02E           PMC[3,0]   2
>>         0x003           PMC3        1
>>
>> Then, it schedules in increasing weight order. So it will
>> schedule weight 1, 2, 3. For weight 1, it will find counter3,
>> for weight 2, it will take counter0, for  weight 3, it will
>> take counter 1 given 0 is already used.
>>
>> Or am I reading your example the wrong way?
>
> No, I have to admit this one was taken out of my mind and I picked
> a wrong example for the special problem I was thinking about. The
> above works as you described because of the constraint's weights.
>
> I don't have an example with existing constraints, but consider the
> following (theoretical) one:
>
> counter: 3210           Failure:        Solution:
>
> e1         xx             xo              ox
> e2        xx             xo              ox
> e3       x x            o x             o x
> e4       x  x           x  F            x  o
>
> The special with the above is that two events (e1 and e2) must be
> rescheduled to schedule e4. This means that swapping counters of only
> one already scheduled event is not sufficient. A counter of a third
> event must be freed, this counter is then taken by the second event.

Ok, I understand this one better now. But you admit yourself, you made it
up. Is it even possible with Fam15h?

The thing is, I think, this is not a catastrophic problem. What will
happen is that
e4 cannot be scheduled with e1, e2, e3. In case the events are not in the same
group, e4 will eventually get a chance to be scheduled due to round-robin on
the event list. In case, the events are all in one group, then you won't be able
to add e4 to the group because of group scheduling sanity check on creation.
So either you have to shuffle your event groups or you will incur multiplexing.
It's not like e4 will be created but it will nerver be able to count anything.



>> The fact that counter have overlapping constraints
>> should not matter. In fact this is what happens with
>> counters without constraints.
>
> An event set containing constraints with following conditions is
> problematic:
>
>  (c1->weight <= c2->weight && (c1->cmask & c2->cmask != c1->cmask))
>
> Basically this means both constraints do not overlap completly. You
> can't select then the correct counter without knowing the events with
> higher weights that will be scheduled later.
>
> -Robert
>
> --
> Advanced Micro Devices, Inc.
> Operating System Research Center
>
>

  reply	other threads:[~2011-04-17  9:06 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-04-16  0:27 [PATCH 0/4] perf, x86: Fixes for v2.6.39 Robert Richter
2011-04-16  0:27 ` [PATCH 1/4] perf, x86: Fix pre-defined cache-misses event for AMD family 15h cpus Robert Richter
2011-04-19 12:03   ` [tip:perf/urgent] " tip-bot for Andre Przywara
2011-04-16  0:27 ` [PATCH 2/4] perf, x86: Fix AMD family 15h FPU event constraints Robert Richter
2011-04-19 12:04   ` [tip:perf/urgent] " tip-bot for Robert Richter
2011-04-16  0:27 ` [PATCH 3/4] perf, x86: Use ALTERNATIVE() to check for X86_FEATURE_PERFCTR_CORE Robert Richter
2011-04-18 20:00   ` Andi Kleen
2011-04-19 10:39     ` Robert Richter
2011-04-19 18:21       ` Andi Kleen
2011-04-19 12:04   ` [tip:perf/core] " tip-bot for Robert Richter
2011-04-16  0:27 ` [PATCH 4/4] perf, x86: Fix event scheduler to solve complex scheduling problems Robert Richter
2011-04-16  8:51   ` Peter Zijlstra
2011-04-16  9:43     ` Ingo Molnar
2011-04-16 10:08       ` Peter Zijlstra
2011-04-16 10:14         ` Ingo Molnar
2011-04-16 10:15           ` Peter Zijlstra
2011-04-16 14:26         ` Valdis.Kletnieks
2011-04-17  8:15     ` Robert Richter
2011-04-17  8:18       ` Ingo Molnar
2011-04-17  8:53         ` Peter Zijlstra
2011-04-17 11:23           ` Robert Richter
2011-04-18  8:17             ` Robert Richter
2011-04-16 15:52   ` Stephane Eranian
2011-04-17  8:44     ` Robert Richter
2011-04-17  9:05       ` Stephane Eranian [this message]
2011-04-19 10:26   ` [PATCH v2] perf, x86: Fix event scheduler for constraints with overlapping counters Robert Richter
2011-04-19 11:29     ` Ingo Molnar
2011-04-19 13:55       ` Robert Richter
2011-04-28  9:50         ` Robert Richter
2011-05-18 21:16     ` Peter Zijlstra
2011-05-18 21:20       ` Ingo Molnar
2011-05-18 21:36         ` Peter Zijlstra
2011-05-19 10:49           ` Robert Richter
2011-05-19 18:06           ` Ingo Molnar
2011-05-20  3:18             ` Robert Richter
2011-09-01 12:56               ` Peter Zijlstra
2011-09-01 14:12                 ` Robert Richter
2011-09-01 16:37                   ` Peter Zijlstra

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