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From: Blue Swirl <blauwirbel@gmail.com>
Date: Fri, 20 May 2011 20:30:07 +0300
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Subject: Re: [Qemu-devel] [RFC] Memory API
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To: Jan Kiszka <jan.kiszka@web.de>
Cc: Peter Maydell <peter.maydell@linaro.org>, Avi Kivity <avi@redhat.com>, Gleb Natapov <gleb@redhat.com>, qemu-devel <qemu-devel@nongnu.org>

On Thu, May 19, 2011 at 11:30 AM, Jan Kiszka <jan.kiszka@web.de> wrote:
> On 2011-05-19 10:26, Gleb Natapov wrote:
>> On Wed, May 18, 2011 at 09:27:55PM +0200, Jan Kiszka wrote:
>>>> if an I/O is to the APIC page,
>>>> =C2=A0 =C2=A0it's handled by the APIC
>>>
>>> That's not that simple. We need to tell apart:
>>> =C2=A0- if a cpu issued the request, and which one =3D> forward to APIC
>> And cpu mode may affect where access is forwarded to. If cpu is in SMM
>> mode access to frame buffer may be forwarded to a memory (depends on
>> chipset configuration).
>
> So we have a second use case for CPU-local I/O regions?

SuperSparc MXCC (memory cache controller) should be CPU specific.
Currently we handle this for accesses via ASI, but the registers could
be mapped with MMU and then the ASI-less access would not be handled.

Another case would be the cache-as-ram mode for some x86 CPUs, which
Coreboot people would like to see IIRC.