[U-Boot] [PATCH v3 3/4] MX5: Introduce a function for setting the chip select size

[Fabio Estevam <festevam@gmail.com>]

Hi Stefano,

On Thu, May 19, 2011 at 5:46 AM, Stefano Babic <sbabic@denx.de> wrote:
> On 05/18/2011 10:47 PM, Fabio Estevam wrote:
>> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
>> ---
>
> Hi Fabio,
>
>> +void set_chipselect_size(int const cs_size)
>> +{
>> + ? ? unsigned int reg;
>> + ? ? struct iomuxc *iomuxc_regs = (struct weim *)IOMUXC_BASE_ADDR;
>> + ? ? reg = readl(&iomuxc_regs->gpr1);
>> +
>> + ? ? switch (cs_size) {
>> + ? ? case CS0_128:
>> + ? ? ? ? ? ? reg &= ~0x7; ? ?/* CS0=128MB, CS1=0, CS2=0, CS3=0 */
>> + ? ? ? ? ? ? reg |= 0x5;
>> + ? ? ? ? ? ? break;
>> + ? ? case CS0_64M_CS1_64M:
>> + ? ? ? ? ? ? reg &= ~0x3F; ? /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
>> + ? ? ? ? ? ? reg |= 0x1B;
>> + ? ? ? ? ? ? break;
>> + ? ? case CS0_64M_CS1_32M_CS2_32M:
>> + ? ? ? ? ? ? reg &= ~0x1FF; ?/* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
>> + ? ? ? ? ? ? reg |= 0x4B;
>> + ? ? ? ? ? ? break;
>> + ? ? case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
>> + ? ? ? ? ? ? reg &= ~0xFFF; ?/* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
>> + ? ? ? ? ? ? reg |= 0x249;
>> + ? ? ? ? ? ? break;
>> + ? ? default:
>> + ? ? ? ? ? ? printf("Unknown chip select size\n");
>> + ? ? ? ? ? ? break;
>> + ? ? }
>> +
>> + ? ? writel(reg, &iomuxc_regs->gpr1);
>> +}
>
> mmmhhh...it seems to me not complete, because not all combinations are
> covered.

Yes, it is complete. Only these four combinations are allowed as per
the MX53 Reference Manual.

>And setting fixed values in the switch constraints us to have
> very long defines, as CS0_32M_CS1_32M_CS2_32M_CS3_32M.

I can change the very long defines if you want.

I thought initially on doing the generic function as you described,
but then we would need to check for only the 4 valid combinations.
Then I came with this implementation that only handle the 4 possible
cases.

Let me know what you think.

Regards,

Fabio Estevam