From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:39604) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QN4Xy-0006A0-Ec for qemu-devel@nongnu.org; Thu, 19 May 2011 10:49:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QN4Xx-000359-D6 for qemu-devel@nongnu.org; Thu, 19 May 2011 10:49:54 -0400 Received: from mail-iw0-f173.google.com ([209.85.214.173]:41512) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QN4Xx-00034n-A8 for qemu-devel@nongnu.org; Thu, 19 May 2011 10:49:53 -0400 Received: by iwl42 with SMTP id 42so2659758iwl.4 for ; Thu, 19 May 2011 07:49:51 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <20110519092428.GA20688@edde.se.axis.com> References: <4DD3C5B9.1080908@redhat.com> <4DD3D236.90708@siemens.com> <4DD3D95E.2060105@redhat.com> <4DD3E1B3.3020405@siemens.com> <4DD3E47F.9060104@redhat.com> <4DD3E782.8090208@siemens.com> <4DD3E8D6.6090807@redhat.com> <20110519090851.GD28399@redhat.com> <20110519092428.GA20688@edde.se.axis.com> Date: Thu, 19 May 2011 15:49:51 +0100 Message-ID: From: Peter Maydell Content-Type: text/plain; charset=UTF-8 Subject: Re: [Qemu-devel] [RFC] Memory API List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Edgar E. Iglesias" Cc: Jan Kiszka , Avi Kivity , Gleb Natapov , qemu-devel On 19 May 2011 10:24, Edgar E. Iglesias wrote: > On the CPU local aspect, I think it is increasingly common in the > embedded space to see local busses with CPU local peripherals in > addition to the "system" bus with "global" peripherals. Yes: newer ARM cores have per-CPU builtin peripherals (timers and the like). The interrupt controller also typically has some registers which are per-CPU and some which are global. At the moment these are rather weirdly placed outside the CPU and it's the obligation of the board model to instantiate them. (Cache modelling would also require a bit more care about the distinction between which core made a memory request and where per-core peripherals live in the cache hierarchy.) The other sort-of-per-core thing is that for TrustZone (which we don't currently support but might want to) if a core is in 'secure' mode it can potentially see a completely different memory map. [In hardware this works by the secure/nonsecure bit being passed around with memory transactions and devices or fabric behaving differently depending on its value.] It would also be nice if the APIs supported more heterogenous setups (for instance a VersatileExpress model where we model a quad core A9 main CPU and also the M3 microcontroller that does system control and has a completely different view of the world.) > Another thing that was discussed was the ability for devices to know > who is accessing them, I think this is uncommon but still it does > exist. Yes, again the ARM GIC is an example. At the momemnt this is implemented by the GIC implementation looking at cpu_single_env->cpu_index. Debug setups also sometimes have magic peripherals that behave differently depending on who is accessing them. -- PMM