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Fri, 5 Feb 2021 00:29:35 +0000 From: Damien Le Moal To: "robh@kernel.org" CC: "paul.walmsley@sifive.com" , "palmer@dabbelt.com" , "linux-riscv@lists.infradead.org" , Atish Patra , "seanga2@gmail.com" , Anup Patel , "devicetree@vger.kernel.org" Subject: Re: [PATCH v14 07/16] dt-bindings: fix sifive gpio properties Thread-Topic: [PATCH v14 07/16] dt-bindings: fix sifive gpio properties Thread-Index: AQHW+U9T59FA/s8Z20mcfAvTuPFEfg== Date: Fri, 5 Feb 2021 00:29:35 +0000 Message-ID: References: <20210202103623.200809-1-damien.lemoal@wdc.com> <20210202103623.200809-8-damien.lemoal@wdc.com> <89cccbae5add85c7bd811f3819ea3db7061e928d.camel@wdc.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: kernel.org; dkim=none (message not signed) header.d=none;kernel.org; dmarc=none action=none header.from=wdc.com; x-originating-ip: [2400:2411:43c0:6000:50f7:ee01:712b:bf92] x-ms-publictraffictype: Email x-ms-office365-filtering-ht: Tenant x-ms-office365-filtering-correlation-id: bcc16cd5-55ea-4fe9-97e6-08d8c96d1d88 x-ms-traffictypediagnostic: MN2PR04MB6894: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: wdcipoutbound: EOP-TRUE x-ms-oob-tlc-oobclassifiers: OLM:10000; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BL0PR04MB6514.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: bcc16cd5-55ea-4fe9-97e6-08d8c96d1d88 X-MS-Exchange-CrossTenant-originalarrivaltime: 05 Feb 2021 00:29:35.5730 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: XRbfEMsY9KMNzh87j4l7Xth4c4ASST4jduSoQNBSFl3xvyeYpLqC2+DdQyXBS+j9UaPLelXJpmL3PLHKqh279g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR04MB6894 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 2021/02/04 9:47, Damien Le Moal wrote:=0A= > On Wed, 2021-02-03 at 14:41 -0600, Rob Herring wrote:=0A= >> On Wed, Feb 3, 2021 at 6:52 AM Damien Le Moal wr= ote:=0A= >>>=0A= >>> On Tue, 2021-02-02 at 13:02 -0600, Rob Herring wrote:=0A= >>>> On Tue, Feb 2, 2021 at 4:36 AM Damien Le Moal = wrote:=0A= >>>>>=0A= >>>>> The sifive gpio IP block supports up to 32 GPIOs. Reflect that in the= =0A= >>>>> interrupts property description and maxItems. Also add the standard= =0A= >>>>> ngpios property to describe the number of GPIOs available on the=0A= >>>>> implementation.=0A= >>>>>=0A= >>>>> Also add the "canaan,k210-gpiohs" compatible string to indicate the u= se=0A= >>>>> of this gpio controller in the Canaan Kendryte K210 SoC. If this=0A= >>>>> compatible string is used, do not define the clocks property as=0A= >>>>> required as the K210 SoC does not have a software controllable clock= =0A= >>>>> for the Sifive gpio IP block.=0A= >>>>>=0A= >>>>> Cc: Paul Walmsley =0A= >>>>> Cc: Rob Herring =0A= >>>>> Cc: devicetree@vger.kernel.org=0A= >>>>> Signed-off-by: Damien Le Moal =0A= >>>>> ---=0A= >>>>> =A0.../devicetree/bindings/gpio/sifive,gpio.yaml | 21 +++++++++++++++= +---=0A= >>>>> =A01 file changed, 18 insertions(+), 3 deletions(-)=0A= >>>>>=0A= >>>>> diff --git a/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml = b/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml=0A= >>>>> index ab22056f8b44..2cef18ca737c 100644=0A= >>>>> --- a/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml=0A= >>>>> +++ b/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml=0A= >>>>> @@ -16,6 +16,7 @@ properties:=0A= >>>>> =A0=A0=A0=A0=A0=A0=A0- enum:=0A= >>>>> =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0- sifive,fu540-c000-gpio=0A= >>>>> =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0- sifive,fu740-c000-gpio=0A= >>>>> + - canaan,k210-gpiohs=0A= >>>>> =A0=A0=A0=A0=A0=A0=A0- const: sifive,gpio0=0A= >>>>>=0A= >>>>> =A0=A0=A0reg:=0A= >>>>> @@ -23,9 +24,9 @@ properties:=0A= >>>>>=0A= >>>>> =A0=A0=A0interrupts:=0A= >>>>> =A0=A0=A0=A0=A0description:=0A= >>>>> - interrupt mapping one per GPIO. Maximum 16 GPIOs.=0A= >>>>> + interrupt mapping one per GPIO. Maximum 32 GPIOs.=0A= >>>>> =A0=A0=A0=A0=A0minItems: 1=0A= >>>>> - maxItems: 16=0A= >>>>> + maxItems: 32=0A= >>>>>=0A= >>>>> =A0=A0=A0interrupt-controller: true=0A= >>>>>=0A= >>>>> @@ -38,6 +39,10 @@ properties:=0A= >>>>> =A0=A0=A0"#gpio-cells":=0A= >>>>> =A0=A0=A0=A0=A0const: 2=0A= >>>>>=0A= >>>>> + ngpios:=0A= >>>>> + minimum: 1=0A= >>>>> + maximum: 32=0A= >>>>=0A= >>>> What's the default as obviously drivers already assume something.=0A= >>>>=0A= >>>> Does a driver actually need to know this? For example, does the=0A= >>>> register stride change or something?=0A= >>>>=0A= >>>> Please don't add it if the only purpose is error check your DT (IOW,= =0A= >>>> if it just checks the max cell value in gpios phandles).=0A= >>>=0A= >>> If I remove that, make dtbs_check complains. Looking at othe gpio contr= oller=0A= >>> bindings, they all have it. So isn't it better to be consistent, and av= oid make=0A= >>> dtbs_check errors ?=0A= >>=0A= >> That would mean you are already using 'ngpios' and it is undocumented=0A= >> (for this binding). If already in use and possibly having users then=0A= >> that changes things, but that's not what the commit msg says.=0A= >>=0A= >> Not *all* gpio controllers have ngpios. It's a good number, but=0A= >> probably more than need it though. If we wanted it everywhere, there=0A= >> would be a schema enforcing that.=0A= > =0A= > If I remove the minimum and maximum lines, I get this error:=0A= > =0A= > ./Documentation/devicetree/bindings/gpio/sifive,gpio.yaml:42:10: [error] = empty=0A= > value in block mapping (empty-values)=0A= > CHKDT Documentation/devicetree/bindings/processed-schema-examples.jso= n=0A= > /home/damien/Projects/RISCV/linux/Documentation/devicetree/bindings/gpio/= sifive=0A= > ,gpio.yaml: properties:ngpios: None is not of type 'object', 'boolean'=0A= > SCHEMA Documentation/devicetree/bindings/processed-schema-examples.jso= n=0A= > /home/damien/Projects/RISCV/linux/Documentation/devicetree/bindings/gpio/= sifive=0A= > ,gpio.yaml: ignoring, error in schema: properties: ngpios=0A= > warning: no schema found in file:=0A= > ./Documentation/devicetree/bindings/gpio/sifive,gpio.yaml=0A= > =0A= > If I remove the ngpios property entirely, then I get a hit on the device = tree:=0A= > =0A= > CHECK arch/riscv/boot/dts/canaan/sipeed_maix_bit.dt.yaml=0A= > /linux/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dt.yaml:=0A= > gpio-controller@38001000: 'ngpios' does not match any of the regexes: 'pi= nctrl-=0A= > [0-9]+'=0A= > From schema:=0A= > /home/damien/Projects/RISCV/linux/Documentation/devicetree/bindings/gpio/= sifive=0A= > ,gpio.yaml=0A= > =0A= > Now, If I change the property definition to this:=0A= > =0A= > diff --git a/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml=0A= > b/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml=0A= > index 2cef18ca737c..5c7865180383 100644=0A= > --- a/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml=0A= > +++ b/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml=0A= > @@ -40,8 +40,11 @@ properties:=0A= > const: 2=0A= > =0A= > ngpios:=0A= > - minimum: 1=0A= > - maximum: 32=0A= > + $ref: /schemas/types.yaml#/definitions/uint32=0A= > + description:=0A= > + The number of GPIO pins implemented by the controller.=0A= > + It is 16 for the SiFive SoCs and 32 for the Canaan K210 SoC.=0A= > +=0A= > =0A= > gpio-controller: true=0A= > =0A= > Then all is OK.=0A= > =0A= > Which option should I go for here ? If we want to avoid a dtbs_check erro= r, as=0A= > far as I can see, we can:=0A= > 1) Remove the ngpios property and remove its use from the DTS, which is n= ot=0A= > nice in my opinion=0A= > 2) Use the modification proposed above=0A= > =0A= > Please advise. Thanks !=0A= > =0A= =0A= Rob,=0A= =0A= Thanks for the reviews and acks on the other patches. I would like to send = v16=0A= with your suggested fixes. But what should I do about ngpios ? Option (1) o= r (2)=0A= above ? Any other option ?=0A= =0A= Thanks !=0A= =0A= -- =0A= Damien Le Moal=0A= Western Digital Research=0A= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,PDS_BAD_THREAD_QP_64,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4CEFBC433DB for ; Fri, 5 Feb 2021 00:29:57 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E046264FAE for ; Fri, 5 Feb 2021 00:29:56 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E046264FAE Authentication-Results: mail.kernel.org; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On 2021/02/04 9:47, Damien Le Moal wrote: > On Wed, 2021-02-03 at 14:41 -0600, Rob Herring wrote: >> On Wed, Feb 3, 2021 at 6:52 AM Damien Le Moal wr= ote: >>> >>> On Tue, 2021-02-02 at 13:02 -0600, Rob Herring wrote: >>>> On Tue, Feb 2, 2021 at 4:36 AM Damien Le Moal = wrote: >>>>> >>>>> The sifive gpio IP block supports up to 32 GPIOs. Reflect that in the >>>>> interrupts property description and maxItems. Also add the standard >>>>> ngpios property to describe the number of GPIOs available on the >>>>> implementation. >>>>> >>>>> Also add the "canaan,k210-gpiohs" compatible string to indicate the u= se >>>>> of this gpio controller in the Canaan Kendryte K210 SoC. If this >>>>> compatible string is used, do not define the clocks property as >>>>> required as the K210 SoC does not have a software controllable clock >>>>> for the Sifive gpio IP block. >>>>> >>>>> Cc: Paul Walmsley >>>>> Cc: Rob Herring >>>>> Cc: devicetree@vger.kernel.org >>>>> Signed-off-by: Damien Le Moal >>>>> --- >>>>> =A0.../devicetree/bindings/gpio/sifive,gpio.yaml | 21 +++++++++++++++= +--- >>>>> =A01 file changed, 18 insertions(+), 3 deletions(-) >>>>> >>>>> diff --git a/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml = b/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml >>>>> index ab22056f8b44..2cef18ca737c 100644 >>>>> --- a/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml >>>>> +++ b/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml >>>>> @@ -16,6 +16,7 @@ properties: >>>>> =A0=A0=A0=A0=A0=A0=A0- enum: >>>>> =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0- sifive,fu540-c000-gpio >>>>> =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0- sifive,fu740-c000-gpio >>>>> + - canaan,k210-gpiohs >>>>> =A0=A0=A0=A0=A0=A0=A0- const: sifive,gpio0 >>>>> >>>>> =A0=A0=A0reg: >>>>> @@ -23,9 +24,9 @@ properties: >>>>> >>>>> =A0=A0=A0interrupts: >>>>> =A0=A0=A0=A0=A0description: >>>>> - interrupt mapping one per GPIO. Maximum 16 GPIOs. >>>>> + interrupt mapping one per GPIO. Maximum 32 GPIOs. >>>>> =A0=A0=A0=A0=A0minItems: 1 >>>>> - maxItems: 16 >>>>> + maxItems: 32 >>>>> >>>>> =A0=A0=A0interrupt-controller: true >>>>> >>>>> @@ -38,6 +39,10 @@ properties: >>>>> =A0=A0=A0"#gpio-cells": >>>>> =A0=A0=A0=A0=A0const: 2 >>>>> >>>>> + ngpios: >>>>> + minimum: 1 >>>>> + maximum: 32 >>>> >>>> What's the default as obviously drivers already assume something. >>>> >>>> Does a driver actually need to know this? For example, does the >>>> register stride change or something? >>>> >>>> Please don't add it if the only purpose is error check your DT (IOW, >>>> if it just checks the max cell value in gpios phandles). >>> >>> If I remove that, make dtbs_check complains. Looking at othe gpio contr= oller >>> bindings, they all have it. So isn't it better to be consistent, and av= oid make >>> dtbs_check errors ? >> >> That would mean you are already using 'ngpios' and it is undocumented >> (for this binding). If already in use and possibly having users then >> that changes things, but that's not what the commit msg says. >> >> Not *all* gpio controllers have ngpios. It's a good number, but >> probably more than need it though. If we wanted it everywhere, there >> would be a schema enforcing that. > = > If I remove the minimum and maximum lines, I get this error: > = > ./Documentation/devicetree/bindings/gpio/sifive,gpio.yaml:42:10: [error] = empty > value in block mapping (empty-values) > CHKDT Documentation/devicetree/bindings/processed-schema-examples.json > /home/damien/Projects/RISCV/linux/Documentation/devicetree/bindings/gpio/= sifive > ,gpio.yaml: properties:ngpios: None is not of type 'object', 'boolean' > SCHEMA Documentation/devicetree/bindings/processed-schema-examples.json > /home/damien/Projects/RISCV/linux/Documentation/devicetree/bindings/gpio/= sifive > ,gpio.yaml: ignoring, error in schema: properties: ngpios > warning: no schema found in file: > ./Documentation/devicetree/bindings/gpio/sifive,gpio.yaml > = > If I remove the ngpios property entirely, then I get a hit on the device = tree: > = > CHECK arch/riscv/boot/dts/canaan/sipeed_maix_bit.dt.yaml > /linux/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dt.yaml: > gpio-controller@38001000: 'ngpios' does not match any of the regexes: 'pi= nctrl- > [0-9]+' > From schema: > /home/damien/Projects/RISCV/linux/Documentation/devicetree/bindings/gpio/= sifive > ,gpio.yaml > = > Now, If I change the property definition to this: > = > diff --git a/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml > b/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml > index 2cef18ca737c..5c7865180383 100644 > --- a/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml > +++ b/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml > @@ -40,8 +40,11 @@ properties: > const: 2 > = > ngpios: > - minimum: 1 > - maximum: 32 > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: > + The number of GPIO pins implemented by the controller. > + It is 16 for the SiFive SoCs and 32 for the Canaan K210 SoC. > + > = > gpio-controller: true > = > Then all is OK. > = > Which option should I go for here ? If we want to avoid a dtbs_check erro= r, as > far as I can see, we can: > 1) Remove the ngpios property and remove its use from the DTS, which is n= ot > nice in my opinion > 2) Use the modification proposed above > = > Please advise. Thanks ! > = Rob, Thanks for the reviews and acks on the other patches. I would like to send = v16 with your suggested fixes. But what should I do about ngpios ? Option (1) o= r (2) above ? Any other option ? Thanks ! -- = Damien Le Moal Western Digital Research _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv