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Tue, 10 Nov 2020 00:35:42 +0000 From: Damien Le Moal To: Rob Herring CC: Serge Semin , Palmer Dabbelt , "linux-riscv@lists.infradead.org" , Frank Rowand , "devicetree@vger.kernel.org" , Mark Brown , "linux-spi@vger.kernel.org" , Stephen Boyd , "linux-clk@vger.kernel.org" , Linus Walleij , "linux-gpio@vger.kernel.org" , Philipp Zabel , Sean Anderson Subject: Re: [PATCH 06/32] spi: dw: Add support for the Kendryte K210 SoC Thread-Topic: [PATCH 06/32] spi: dw: Add support for the Kendryte K210 SoC Thread-Index: AQHWtN4N0wumwRzXdUGPL6nbxUOPpw== Date: Tue, 10 Nov 2020 00:35:42 +0000 Message-ID: References: <20201107081420.60325-1-damien.lemoal@wdc.com> <20201107081420.60325-7-damien.lemoal@wdc.com> <20201109212158.y34otj3uy2hev75c@mobilestation> <20201109215524.GA1819368@bogus> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: kernel.org; dkim=none (message not signed) header.d=none;kernel.org; dmarc=none action=none header.from=wdc.com; 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x-ms-exchange-antispam-messagedata: NKpjHj2fehOVan/eK8DNZmWlXKzmalFITVEZ3a3tfZWMokR6vavbAcGAt12QduJoMy8vPnF/u3EedqX8iFsvC7M+DCw4s9/DHgkEcfcC4TOdXyEQQIT5Z1YoVdUAo9mPD5vwKlkTnqJuUOT+e9e/rXV3tyNimYpGqFZe6+yNiNO5qYzdNs5cAQIwL4sYR9/4Hxysh4Jq1YQuE453fX3tSceLpPF/Rh2cPCfCe/GfCbniBRODCP1Enj4ceU99P0h0RcNl7HX00MRSC4NAFXQZqruI/ouynkxQZDi6o0JZq1MheiH6z9tjbUAmV2UYZo+Auqe61gUYj1WyNRYx5uhvS0B0sjEpex836kQ3zDK8x7o3Jw4tuQzA7J1rlcqnVu0mgzkNQWCgB7Npl5S9S0cDZEhWR2OlzbCMXSxO00DezaJBlWPsNXEeG8IN5RsVUCCFDK12qODi4A/8IbMl3VVTVdlu4F/oPHfqUafZib3KDospg2Y7TPhZLNxSHQ+jQDD5xQr7rttDazyIrLk03wkPQfobycPSqgb9Jhdwrfejp7qeWTXaCiX/t+gp/sgxzpFMY79/8yLV7Qike/PvdJ95I/2AWc++Mi+XqMkQtbq4xkyZMfGH/YZzB8m3hW+Jx+leaJOnRuTQ5Sni0ajhgPSSAg== x-ms-exchange-transport-forked: True Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BL0PR04MB6514.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 59ef60a4-83be-4171-4781-08d885108e56 X-MS-Exchange-CrossTenant-originalarrivaltime: 10 Nov 2020 00:35:42.5949 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: YdE6xqNWfnpkBVEPglyiMFvim+ITTWIo+BXkmq5wC/IqOA8d+KSCDbNlAfr9B1+xJ8mv3STlt/HS8awIgcJGxg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR04MB7071 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org On 2020/11/10 8:08, Rob Herring wrote:=0A= > On Mon, Nov 9, 2020 at 4:00 PM Damien Le Moal wro= te:=0A= >>=0A= >> On 2020/11/10 6:55, Rob Herring wrote:=0A= >>> On Mon, Nov 09, 2020 at 09:39:19PM +0000, Damien Le Moal wrote:=0A= >>>> On 2020/11/10 6:22, Serge Semin wrote:=0A= >>>>> On Sat, Nov 07, 2020 at 05:13:54PM +0900, Damien Le Moal wrote:=0A= >>>>>> The DW SPI master of the Kendryte K210 RISC-V SoC uses the 32-bits= =0A= >>>>>> ctrlr0 register format. This SoC is also quite slow and gets signifi= cant=0A= >>>>>> SD card performance improvements from using no-delay polled transfer= s.=0A= >>>>>> Add the dw_spi_k210_init() function tied to the=0A= >>>>>> "canaan,kendryte-k210-spi" compatible string to set the=0A= >>>>>> DW_SPI_CAP_DFS_32 and DW_SPI_CAP_POLL_NODELAY DW SPI capability fiel= ds=0A= >>>>>> for this SoC.=0A= >>>>>>=0A= >>>>>> Signed-off-by: Damien Le Moal =0A= >>>>>> ---=0A= >>>>>> drivers/spi/spi-dw-mmio.c | 9 +++++++++=0A= >>>>>> 1 file changed, 9 insertions(+)=0A= >>>>>>=0A= >>>>>> diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c= =0A= >>>>>> index 3f1bc384cb45..a00def6c5b39 100644=0A= >>>>>> --- a/drivers/spi/spi-dw-mmio.c=0A= >>>>>> +++ b/drivers/spi/spi-dw-mmio.c=0A= >>>>>> @@ -223,6 +223,14 @@ static int dw_spi_keembay_init(struct platform_= device *pdev,=0A= >>>>>> return 0;=0A= >>>>>> }=0A= >>>>>>=0A= >>>>>> +static int dw_spi_k210_init(struct platform_device *pdev,=0A= >>>>>> + struct dw_spi_mmio *dwsmmio)=0A= >>>>>> +{=0A= >>>>>> + dwsmmio->dws.caps =3D DW_SPI_CAP_DFS_32 | DW_SPI_CAP_POLL_NODELAY= ;=0A= >>>>>> +=0A= >>>>>> + return 0;=0A= >>>>>> +}=0A= >>>>>> +=0A= >>>>>> static int dw_spi_mmio_probe(struct platform_device *pdev)=0A= >>>>>> {=0A= >>>>>> int (*init_func)(struct platform_device *pdev,=0A= >>>>>> @@ -340,6 +348,7 @@ static const struct of_device_id dw_spi_mmio_of_= match[] =3D {=0A= >>>>>> { .compatible =3D "snps,dwc-ssi-1.01a", .data =3D dw_spi_dwc_ssi_= init},=0A= >>>>>> { .compatible =3D "intel,keembay-ssi", .data =3D dw_spi_keembay_i= nit},=0A= >>>>>> { .compatible =3D "microchip,sparx5-spi", dw_spi_mscc_sparx5_init= },=0A= >>>>>=0A= >>>>>> + { .compatible =3D "canaan,kendryte-k210-spi", .data =3D dw_spi_k2= 10_init},=0A= >>>>>=0A= >>>>> Other than the comments from Sean and Mark regarding the DFS_32=0A= >>>>> feature runtime detectability, I couldn't find a patch with adding th= e=0A= >>>>> new new compatible string into the DW APB SSI DT schema. Have I misse= d=0A= >>>>> it? If I haven't could you add one to the next version of the series?= =0A= >>>>=0A= >>>> Yes, I will. I forgot to change the DW DT binding doc for this. I did = add a=0A= >>>> patch for the "polling" property but forgot the compatible string.=0A= >>>>=0A= >>>> In any case, I think that this new compatible string change can be dro= pped by=0A= >>>> switching to automatically detecting the DFS32 and using a different s= olution=0A= >>>> than the polling property change I sent for the RX fifo overflow probl= em.=0A= >>>=0A= >>> No, new SoC needs new compatible string. Especially if a new vendor.=0A= >>=0A= >> My apologies for the bad wording: I meant to say the change to the list = of=0A= >> compatible strings that the DW SPI support would not be needed. So from = the DW=0A= >> SPI point of view, there would be no new compatible string to add/docume= nt.=0A= > =0A= > No, there is a need for a new compatible string to add/document. You=0A= > might not need it in the driver if you have a fallback.=0A= > =0A= > Compatible strings should be SoC specific so you can handle quirks=0A= > without a DT change. Otherwise, it's a never ending stream of new=0A= > properties and DT updates.=0A= =0A= Ah. OK. I get it now. Thanks for clarifying. So I will keep the new compati= ble=0A= string (renamed with proper vendor name instead of brand) and document it.= =0A= =0A= > =0A= >>>> I am still going through all the emails trying to understand what to t= ry next to=0A= >>>> avoid the polling "hack".=0A= >>>=0A= >>> Use compatible.=0A= >>=0A= >> Yes, that is what this patch used. Again, I think there is a chance this= change=0A= >> can be dropped.=0A= > =0A= > Looks to me like it used a 'polling' property...=0A= =0A= I hope to be able to get rid of this change if a proper solution can be fou= nd to=0A= the transfer speed problem I am seeing.=0A= =0A= > =0A= > Rob=0A= > =0A= =0A= =0A= -- =0A= Damien Le Moal=0A= Western Digital Research=0A= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53B66C2D0A3 for ; Tue, 10 Nov 2020 00:36:04 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8092D206D8 for ; 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Tue, 10 Nov 2020 00:35:42 +0000 From: Damien Le Moal To: Rob Herring Subject: Re: [PATCH 06/32] spi: dw: Add support for the Kendryte K210 SoC Thread-Topic: [PATCH 06/32] spi: dw: Add support for the Kendryte K210 SoC Thread-Index: AQHWtN4N0wumwRzXdUGPL6nbxUOPpw== Date: Tue, 10 Nov 2020 00:35:42 +0000 Message-ID: References: <20201107081420.60325-1-damien.lemoal@wdc.com> <20201107081420.60325-7-damien.lemoal@wdc.com> <20201109212158.y34otj3uy2hev75c@mobilestation> <20201109215524.GA1819368@bogus> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: kernel.org; dkim=none (message not signed) header.d=none;kernel.org; dmarc=none action=none header.from=wdc.com; x-originating-ip: [129.253.182.55] x-ms-publictraffictype: Email x-ms-office365-filtering-ht: Tenant x-ms-office365-filtering-correlation-id: 59ef60a4-83be-4171-4781-08d885108e56 x-ms-traffictypediagnostic: MN2PR04MB7071: x-microsoft-antispam-prvs: wdcipoutbound: EOP-TRUE x-ms-oob-tlc-oobclassifiers: OLM:10000; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On 2020/11/10 8:08, Rob Herring wrote: > On Mon, Nov 9, 2020 at 4:00 PM Damien Le Moal wrote: >> >> On 2020/11/10 6:55, Rob Herring wrote: >>> On Mon, Nov 09, 2020 at 09:39:19PM +0000, Damien Le Moal wrote: >>>> On 2020/11/10 6:22, Serge Semin wrote: >>>>> On Sat, Nov 07, 2020 at 05:13:54PM +0900, Damien Le Moal wrote: >>>>>> The DW SPI master of the Kendryte K210 RISC-V SoC uses the 32-bits >>>>>> ctrlr0 register format. This SoC is also quite slow and gets significant >>>>>> SD card performance improvements from using no-delay polled transfers. >>>>>> Add the dw_spi_k210_init() function tied to the >>>>>> "canaan,kendryte-k210-spi" compatible string to set the >>>>>> DW_SPI_CAP_DFS_32 and DW_SPI_CAP_POLL_NODELAY DW SPI capability fields >>>>>> for this SoC. >>>>>> >>>>>> Signed-off-by: Damien Le Moal >>>>>> --- >>>>>> drivers/spi/spi-dw-mmio.c | 9 +++++++++ >>>>>> 1 file changed, 9 insertions(+) >>>>>> >>>>>> diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c >>>>>> index 3f1bc384cb45..a00def6c5b39 100644 >>>>>> --- a/drivers/spi/spi-dw-mmio.c >>>>>> +++ b/drivers/spi/spi-dw-mmio.c >>>>>> @@ -223,6 +223,14 @@ static int dw_spi_keembay_init(struct platform_device *pdev, >>>>>> return 0; >>>>>> } >>>>>> >>>>>> +static int dw_spi_k210_init(struct platform_device *pdev, >>>>>> + struct dw_spi_mmio *dwsmmio) >>>>>> +{ >>>>>> + dwsmmio->dws.caps = DW_SPI_CAP_DFS_32 | DW_SPI_CAP_POLL_NODELAY; >>>>>> + >>>>>> + return 0; >>>>>> +} >>>>>> + >>>>>> static int dw_spi_mmio_probe(struct platform_device *pdev) >>>>>> { >>>>>> int (*init_func)(struct platform_device *pdev, >>>>>> @@ -340,6 +348,7 @@ static const struct of_device_id dw_spi_mmio_of_match[] = { >>>>>> { .compatible = "snps,dwc-ssi-1.01a", .data = dw_spi_dwc_ssi_init}, >>>>>> { .compatible = "intel,keembay-ssi", .data = dw_spi_keembay_init}, >>>>>> { .compatible = "microchip,sparx5-spi", dw_spi_mscc_sparx5_init}, >>>>> >>>>>> + { .compatible = "canaan,kendryte-k210-spi", .data = dw_spi_k210_init}, >>>>> >>>>> Other than the comments from Sean and Mark regarding the DFS_32 >>>>> feature runtime detectability, I couldn't find a patch with adding the >>>>> new new compatible string into the DW APB SSI DT schema. Have I missed >>>>> it? If I haven't could you add one to the next version of the series? >>>> >>>> Yes, I will. I forgot to change the DW DT binding doc for this. I did add a >>>> patch for the "polling" property but forgot the compatible string. >>>> >>>> In any case, I think that this new compatible string change can be dropped by >>>> switching to automatically detecting the DFS32 and using a different solution >>>> than the polling property change I sent for the RX fifo overflow problem. >>> >>> No, new SoC needs new compatible string. Especially if a new vendor. >> >> My apologies for the bad wording: I meant to say the change to the list of >> compatible strings that the DW SPI support would not be needed. So from the DW >> SPI point of view, there would be no new compatible string to add/document. > > No, there is a need for a new compatible string to add/document. You > might not need it in the driver if you have a fallback. > > Compatible strings should be SoC specific so you can handle quirks > without a DT change. Otherwise, it's a never ending stream of new > properties and DT updates. Ah. OK. I get it now. Thanks for clarifying. So I will keep the new compatible string (renamed with proper vendor name instead of brand) and document it. > >>>> I am still going through all the emails trying to understand what to try next to >>>> avoid the polling "hack". >>> >>> Use compatible. >> >> Yes, that is what this patch used. Again, I think there is a chance this change >> can be dropped. > > Looks to me like it used a 'polling' property... I hope to be able to get rid of this change if a proper solution can be found to the transfer speed problem I am seeing. > > Rob > -- Damien Le Moal Western Digital Research _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv