From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Lu, Wei" Subject: Re: [PATCH] drm/amdgpu: change pp_dpm clk/mclk/pcie input format Date: Tue, 24 Apr 2018 13:22:22 +0000 Message-ID: References: <1524171079-657-1-git-send-email-wei.lu2@amd.com>, Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0728709051==" Return-path: In-Reply-To: Content-Language: en-GB List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "amd-gfx" To: Alex Deucher Cc: amd-gfx list --===============0728709051== Content-Language: en-GB Content-Type: multipart/alternative; boundary="_000_BL0PR12MB2387B639AC81E7F2E6007490A3880BL0PR12MB2387namp_" --_000_BL0PR12MB2387B639AC81E7F2E6007490A3880BL0PR12MB2387namp_ Content-Type: text/plain; charset="iso-2022-jp" Content-Transfer-Encoding: quoted-printable hi Alex, I have sent the patch with "Add: DOC " and last patch to amd-gfx-PD4FTy7X32mzQB+pC5nmwQ@public.gmane.org= edesktop.org already. please check. Thanks! Wei ________________________________ From: Alex Deucher Sent: 23 April 2018 16:06:16 To: Lu, Wei Cc: amd-gfx list Subject: Re: [PATCH] drm/amdgpu: change pp_dpm clk/mclk/pcie input format On Thu, Apr 19, 2018 at 4:51 PM, welu wrote: > 1. support more than 8 values when setting get_pp_dpm_mclk/ > sclk/pcie, the former design just parse command format like > "echo xxxx >=1B$B!!=1B(Bpp_dpm_sclk" and current can parse "echo xx xxx > xxxx > pp_dpm_sclk" whose operation is more user-friendly > and convinent and can offer more values; > 2. be compatible with former design like "xx". > Bug:KFD-385 Please update the documentation labeled "DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_pcie", With that fixed, patch is: Reviewed-by: Alex Deucher > > Change-Id: Id7d95ce45f4ee0564b18ebcfc16976f1a5c6bf72 > Signed-off-by: welu > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 95 ++++++++++++++++++++--------= ------ > 1 file changed, 55 insertions(+), 40 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd= /amdgpu/amdgpu_pm.c > index 744f105..58f46f9 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c > @@ -466,23 +466,27 @@ static ssize_t amdgpu_set_pp_dpm_sclk(struct device= *dev, > struct amdgpu_device *adev =3D ddev->dev_private; > int ret; > long level; > - uint32_t i, mask =3D 0; > - char sub_str[2]; > + uint32_t mask =3D 0; > + char *sub_str =3D NULL; > + char *tmp; > + char buf_cpy[count]; > + const char delimiter[3] =3D {' ', '\n', '\0'}; > > - for (i =3D 0; i < strlen(buf); i++) { > - if (*(buf + i) =3D=3D '\n') > - continue; > - sub_str[0] =3D *(buf + i); > - sub_str[1] =3D '\0'; > - ret =3D kstrtol(sub_str, 0, &level); > + memcpy(buf_cpy, buf, count+1); > + tmp =3D buf_cpy; > + while (tmp[0]) { > + sub_str =3D strsep(&tmp, delimiter); > + if (strlen(sub_str)) { > + ret =3D kstrtol(sub_str, 0, &level); > > - if (ret) { > - count =3D -EINVAL; > - goto fail; > - } > - mask |=3D 1 << level; > + if (ret) { > + count =3D -EINVAL; > + goto fail; > + } > + mask |=3D 1 << level; > + } else > + break; > } > - > if (adev->powerplay.pp_funcs->force_clock_level) > amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask); > > @@ -512,21 +516,26 @@ static ssize_t amdgpu_set_pp_dpm_mclk(struct device= *dev, > struct amdgpu_device *adev =3D ddev->dev_private; > int ret; > long level; > - uint32_t i, mask =3D 0; > - char sub_str[2]; > + uint32_t mask =3D 0; > + char *sub_str =3D NULL; > + char *tmp; > + char buf_cpy[count]; > + const char delimiter[3] =3D {' ', '\n', '\0'}; > > - for (i =3D 0; i < strlen(buf); i++) { > - if (*(buf + i) =3D=3D '\n') > - continue; > - sub_str[0] =3D *(buf + i); > - sub_str[1] =3D '\0'; > - ret =3D kstrtol(sub_str, 0, &level); > + memcpy(buf_cpy, buf, count+1); > + tmp =3D buf_cpy; > + while (tmp[0]) { > + sub_str =3D strsep(&tmp, delimiter); > + if (strlen(sub_str)) { > + ret =3D kstrtol(sub_str, 0, &level); > > - if (ret) { > - count =3D -EINVAL; > - goto fail; > - } > - mask |=3D 1 << level; > + if (ret) { > + count =3D -EINVAL; > + goto fail; > + } > + mask |=3D 1 << level; > + } else > + break; > } > if (adev->powerplay.pp_funcs->force_clock_level) > amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask); > @@ -557,21 +566,27 @@ static ssize_t amdgpu_set_pp_dpm_pcie(struct device= *dev, > struct amdgpu_device *adev =3D ddev->dev_private; > int ret; > long level; > - uint32_t i, mask =3D 0; > - char sub_str[2]; > + uint32_t mask =3D 0; > + char *sub_str =3D NULL; > + char *tmp; > + char buf_cpy[count]; > + const char delimiter[3] =3D {' ', '\n', '\0'}; > > - for (i =3D 0; i < strlen(buf); i++) { > - if (*(buf + i) =3D=3D '\n') > - continue; > - sub_str[0] =3D *(buf + i); > - sub_str[1] =3D '\0'; > - ret =3D kstrtol(sub_str, 0, &level); > + memcpy(buf_cpy, buf, count+1); > + tmp =3D buf_cpy; > > - if (ret) { > - count =3D -EINVAL; > - goto fail; > - } > - mask |=3D 1 << level; > + while (tmp[0]) { > + sub_str =3D strsep(&tmp, delimiter); > + if (strlen(sub_str)) { > + ret =3D kstrtol(sub_str, 0, &level); > + > + if (ret) { > + count =3D -EINVAL; > + goto fail; > + } > + mask |=3D 1 << level; > + } else > + break; > } > if (adev->powerplay.pp_funcs->force_clock_level) > amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask); > -- > 2.7.4 > > _______________________________________________ > amd-gfx mailing list > amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx --_000_BL0PR12MB2387B639AC81E7F2E6007490A3880BL0PR12MB2387namp_ Content-Type: text/html; charset="iso-2022-jp" Content-Transfer-Encoding: quoted-printable

hi Alex,


I have sent the patch with "= Add: DOC " and last patch to  amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org already.

please check.


Thanks!


Wei

From: Alex Deucher <alex= deucher-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Sent: 23 April 2018 16:06:16
To: Lu, Wei
Cc: amd-gfx list
Subject: Re: [PATCH] drm/amdgpu: change pp_dpm clk/mclk/pcie input f= ormat
 
On Thu, Apr 19, 2018 at 4:51 PM, welu <wei.lu2@= amd.com> wrote:
> 1. support more than 8 values when setting get_pp_dpm_mclk/
> sclk/pcie, the former design just parse command format like
> "echo xxxx >=1B$B!!=1B(Bpp_dpm_sclk" and current can pars= e "echo xx xxx
>  xxxx > pp_dpm_sclk" whose operation is more user-friendl= y
> and convinent and can offer more values;
> 2. be compatible with former design like "xx".
> Bug:KFD-385

Please update the documentation labeled "DOC: pp_dpm_sclk pp_dpm_mclk<= br> pp_dpm_pcie", With that fixed, patch is:
Reviewed-by: Alex Deucher <alexander.deucher-5C7GfCeVMHo@public.gmane.org>

>
> Change-Id: Id7d95ce45f4ee0564b18ebcfc16976f1a5c6bf72
> Signed-off-by: welu <wei.lu2-5C7GfCeVMHo@public.gmane.org>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 95 ++++= +++++++++++++++= +--------------
>  1 file changed, 55 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/= amd/amdgpu/amdgpu_pm.c
> index 744f105..58f46f9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> @@ -466,23 +466,27 @@ static ssize_t amdgpu_set_pp_dpm_sclk(struct= device *dev,
>         struct amdgpu_device *= adev =3D ddev->dev_private;
>         int ret;
>         long level;
> -       uint32_t i, mask =3D 0;
> -       char sub_str[2];
> +       uint32_t mask =3D 0;
> +       char *sub_str =3D NULL;
> +       char *tmp;
> +       char buf_cpy[count];
> +       const char delimiter[3] =3D = {' ', '\n', '\0'};
>
> -       for (i =3D 0; i < strlen(buf)= ; i++) {
> -           &nb= sp;   if (*(buf + i) =3D=3D '\n')
> -           &nb= sp;           continue; > -           &nb= sp;   sub_str[0] =3D *(buf + i);
> -           &nb= sp;   sub_str[1] =3D '\0';
> -           &nb= sp;   ret =3D kstrtol(sub_str, 0, &level);
> +       memcpy(buf_cpy, buf, count&#= 43;1);
> +       tmp =3D buf_cpy;
> +       while (tmp[0]) {
> +           = ;    sub_str =3D  strsep(&tmp, delimiter);
> +           = ;    if (strlen(sub_str)) {
> +           = ;            ret =3D= kstrtol(sub_str, 0, &level);
>
> -           &nb= sp;   if (ret) {
> -           &nb= sp;           count =3D -= EINVAL;
> -           &nb= sp;           goto fail;<= br> > -           &nb= sp;   }
> -           &nb= sp;   mask |=3D 1 << level;
> +           = ;            if (ret= ) {
> +           = ;            &n= bsp;       count =3D -EINVAL;
> +           = ;            &n= bsp;       goto fail;
> +           = ;            }
> +           = ;            mask |= =3D 1 << level;
> +           = ;    } else
> +           = ;            break;<= br> >         }
> -
>         if (adev->powerplay= .pp_funcs->force_clock_level)
>            = ;     amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask)= ;
>
> @@ -512,21 +516,26 @@ static ssize_t amdgpu_set_pp_dpm_mclk(struct= device *dev,
>         struct amdgpu_device *= adev =3D ddev->dev_private;
>         int ret;
>         long level;
> -       uint32_t i, mask =3D 0;
> -       char sub_str[2];
> +       uint32_t mask =3D 0;
> +       char *sub_str =3D NULL;
> +       char *tmp;
> +       char buf_cpy[count];
> +       const char delimiter[3] =3D = {' ', '\n', '\0'};
>
> -       for (i =3D 0; i < strlen(buf)= ; i++) {
> -           &nb= sp;   if (*(buf + i) =3D=3D '\n')
> -           &nb= sp;           continue; > -           &nb= sp;   sub_str[0] =3D *(buf + i);
> -           &nb= sp;   sub_str[1] =3D '\0';
> -           &nb= sp;   ret =3D kstrtol(sub_str, 0, &level);
> +       memcpy(buf_cpy, buf, count&#= 43;1);
> +       tmp =3D buf_cpy;
> +       while (tmp[0]) {
> +           = ;    sub_str =3D  strsep(&tmp, delimiter);
> +           = ;    if (strlen(sub_str)) {
> +           = ;            ret =3D= kstrtol(sub_str, 0, &level);
>
> -           &nb= sp;   if (ret) {
> -           &nb= sp;           count =3D -= EINVAL;
> -           &nb= sp;           goto fail;<= br> > -           &nb= sp;   }
> -           &nb= sp;   mask |=3D 1 << level;
> +           = ;            if (ret= ) {
> +           = ;            &n= bsp;       count =3D -EINVAL;
> +           = ;            &n= bsp;       goto fail;
> +           = ;            }
> +           = ;            mask |= =3D 1 << level;
> +           = ;    } else
> +           = ;            break;<= br> >         }
>         if (adev->powerplay= .pp_funcs->force_clock_level)
>            = ;     amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask)= ;
> @@ -557,21 +566,27 @@ static ssize_t amdgpu_set_pp_dpm_pcie(struct= device *dev,
>         struct amdgpu_device *= adev =3D ddev->dev_private;
>         int ret;
>         long level;
> -       uint32_t i, mask =3D 0;
> -       char sub_str[2];
> +       uint32_t mask =3D 0;
> +       char *sub_str =3D NULL;
> +       char *tmp;
> +       char buf_cpy[count];
> +       const char delimiter[3] =3D = {' ', '\n', '\0'};
>
> -       for (i =3D 0; i < strlen(buf)= ; i++) {
> -           &nb= sp;   if (*(buf + i) =3D=3D '\n')
> -           &nb= sp;           continue; > -           &nb= sp;   sub_str[0] =3D *(buf + i);
> -           &nb= sp;   sub_str[1] =3D '\0';
> -           &nb= sp;   ret =3D kstrtol(sub_str, 0, &level);
> +       memcpy(buf_cpy, buf, count&#= 43;1);
> +       tmp =3D buf_cpy;
>
> -           &nb= sp;   if (ret) {
> -           &nb= sp;           count =3D -= EINVAL;
> -           &nb= sp;           goto fail;<= br> > -           &nb= sp;   }
> -           &nb= sp;   mask |=3D 1 << level;
> +       while (tmp[0]) {
> +           = ;    sub_str =3D  strsep(&tmp, delimiter);
> +           = ;    if (strlen(sub_str)) {
> +           = ;            ret =3D= kstrtol(sub_str, 0, &level);
> +
> +           = ;            if (ret= ) {
> +           = ;            &n= bsp;       count =3D -EINVAL;
> +           = ;            &n= bsp;       goto fail;
> +           = ;            }
> +           = ;            mask |= =3D 1 << level;
> +           = ;    } else
> +           = ;            break;<= br> >         }
>         if (adev->powerplay= .pp_funcs->force_clock_level)
>            = ;     amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask)= ;
> --
> 2.7.4
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> htt= ps://lists.freedesktop.org/mailman/listinfo/amd-gfx
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