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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Background: The ia-32/ia-64 fxsave64 instruction saves fp80 or legacy SSE m= mx registers. The mmx registers are saved as if they were fp80 values. The = lower 64 bits of the constructed fp80 value is the mmx register. The upper= 16 bits of the constructed fp80 value are reserved; see the last row of ta= ble 3-44 of https://www.felixcloutier.com/x86/fxsave#tbl-3-44 The Intel core i9-9980XE Skylake metal I have puts 0xffff into these reserv= ed 16 bits when saving MMX. QEMU appears to put 0's there. Does anybody have insight as to what "reserved" really means, or must be, i= n this case? I take the verb "reserved" to mean something other than "unde= fined". I came across this issue when running the remill instruction test engine. = See my issue https://github.com/lifting-bits/remill/issues/423 For better o= r worse, remill assumes that those bits are 0xffff, not 0x0000 --_000_BL0PR2101MB1026B7400F5A568C9D5FC9DBD68F0BL0PR2101MB1026_ Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable
Background: The ia-32/ia-64 fxsave64 instruction saves fp80 or legacy SSE m= mx registers. The mmx registers are saved as if they were fp80 values. The = lower 64 bits of the constructed fp80 value is the mmx register.  The = upper 16 bits of the constructed fp80 value are reserved; see the last row of table 3-44 of https://= www.felixcloutier.com/x86/fxsave#tbl-3-44

The Intel core i9-9980XE Skylake metal I have puts 0xffff into these reserv= ed 16 bits when saving MMX.

QEMU appears to put 0's there.

Does anybody have insight as to what "reserved" really means, or = must be, in this case?  I take the verb "reserved" to mean s= omething other than "undefined".

I came across this issue when running the remill instruction test engine.&n= bsp; See my issue https://github.com/lifting-bits/remill/issues/423 Fo= r better or worse, remill assumes that those bits are 0xffff, not 0x0000

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