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Thu, 10 Feb 2022 05:36:06 +0000 From: "Liu, Chuansheng" To: "Roper, Matthew D" Thread-Topic: [PATCH] drm/i915/dg1: Update DMC_DEBUG3 register Thread-Index: AQHYHj7rbwTxu4Kemkq/ajAoX/7QNKyMQkxg Date: Thu, 10 Feb 2022 05:36:06 +0000 Message-ID: References: <20220210050501.87795-1-chuansheng.liu@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.6.200.16 authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: dd659144-99f3-4654-1c7f-08d9ec573c6c x-ms-traffictypediagnostic: BN0PR11MB5744:EE_ x-ld-processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:2512; x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: FziDG7CTXuXHUMlvuVB5+GZvHyeTiquhm8O1yHdc3LLAPmRaRwq3T0VtmeM4ddtugTV0r1CuQeB6HNOBViw93yMckvSyTHCpQzsAqYf/qxDrSrEvnCT4IdEONqkaHnU0GxY5Fy7BVodwvwh3p7FwpwKWeU83bbEKw7SQCXlUmtMldFJPd7leQWnNv08Q0O9A9kmIWUCI2/j76YAd3l58f7IgwuCdZI6gpzzmRfREREUo2KSj3ouhH7fGw0fD/yx6emniFoKjc6ypjiLRQGvl/taSYbqKntIgiPUas8A2NLYD3YZpoir3YSW3uo+rlCih1ueeV2kQnPOOcmMpcxbt2bQ8f8qcZLqtam3lRhUix3YCYihVc+cShA6xSvUoJ3I5DTPzrmfZqsMde7iYymHeDqAvgx8LdELjr503UADSEud1DYz6QR5fGmN9o5boxCf7UVlOYWFGsCnI8xByh5xcgMfk4uVw1QIKGrFWndd6iCXi4QXkCB8kD7iBmw3U+AimH3S0kjj/yIwUz60H5thzLiU0K02VgMmtooRj4lpTZXbUIPTZZ4/sOrOzcwdcZNajy1db95sWbp5yhxeFAPxeS5hu/hJNMwvnkFfzcC1FY0hGiIF328vB4xO21/lUBDxTSN/wb/afMO2dxE7ACc7TOfDHe8xQ6fM2jd5Tzj4pJ0fi3UkHX4sdofJ8tPL3OZ2IRFkYi12ZyE2kPG2LhOfyiA== x-forefront-antispam-report: CIP:255.255.255.255; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BL1PR11MB5445.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: dd659144-99f3-4654-1c7f-08d9ec573c6c X-MS-Exchange-CrossTenant-originalarrivaltime: 10 Feb 2022 05:36:06.8726 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: kvICI2sLUZGqblP0MmXM0MTdK9lr+LuNbSNakpmjHv9N4ov5Czv3I2l0rxhzZX28NDc430PH/jP6M0mUvoHxY8pQUF/Tn1Vg0zDxsDo1Rfw= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN0PR11MB5744 X-OriginatorOrg: intel.com Subject: Re: [Intel-gfx] [PATCH] drm/i915/dg1: Update DMC_DEBUG3 register X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "intel-gfx@lists.freedesktop.org" , "De Marchi, Lucas" Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" > -----Original Message----- > From: Roper, Matthew D > Sent: Thursday, February 10, 2022 1:28 PM > To: Liu, Chuansheng > Cc: intel-gfx@lists.freedesktop.org; Gupta, Anshuman > ; De Marchi, Lucas > > Subject: Re: [PATCH] drm/i915/dg1: Update DMC_DEBUG3 register >=20 > On Thu, Feb 10, 2022 at 01:05:01PM +0800, Chuansheng Liu wrote: > > Current DMC_DEBUG3(_MMIO(0x101090)) address is for TGL, > > it is not wrong for DG1. Just like commit 5bcc95ca382e > > ("drm/i915/dg1: Update DMC_DEBUG register"), correct > > this issue for DG1 platform to avoid wrong register > > being read. > > > > BSpec: 49788 > > > > Signed-off-by: Chuansheng Liu > > --- > > drivers/gpu/drm/i915/display/intel_display_debugfs.c | 4 ++-- > > drivers/gpu/drm/i915/i915_reg.h | 3 ++- > > 2 files changed, 4 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c > b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > index f4de004d470f..f6c4ad8fce19 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > @@ -474,8 +474,8 @@ static int i915_dmc_info(struct seq_file *m, void > *unused) > > * reg for DC3CO debugging and validation, > > * but TGL DMC f/w is using DMC_DEBUG3 reg for DC3CO > counter. > > */ > > - seq_printf(m, "DC3CO count: %d\n", > > - intel_de_read(dev_priv, DMC_DEBUG3)); > > + seq_printf(m, "DC3CO count: %d\n", intel_de_read(dev_priv, > IS_DGFX(dev_priv) ? > > + DG1_DMC_DEBUG3 : > TGL_DMC_DEBUG3)); >=20 > It looks like some future igpu platforms will likely also use this new Exactly, at that time, the condition check IS_DGFX() should be refined for DMC_DEBUGx registers, so far keep it as so. > register offset, but those are a bit down the road; we can cross that > bridge when we get to it. This change looks correct for now. >=20 > Reviewed-by: Matt Roper Thanks Matt for quick review. >=20 > > } else { > > dc5_reg =3D IS_BROXTON(dev_priv) ? > BXT_DMC_DC3_DC5_COUNT : > > SKL_DMC_DC3_DC5_COUNT; > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > b/drivers/gpu/drm/i915/i915_reg.h > > index 87c92314ee26..9c215a6df659 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -5632,7 +5632,8 @@ > > #define TGL_DMC_DEBUG_DC6_COUNT _MMIO(0x101088) > > #define DG1_DMC_DEBUG_DC5_COUNT _MMIO(0x134154) > > > > -#define DMC_DEBUG3 _MMIO(0x101090) > > +#define TGL_DMC_DEBUG3 _MMIO(0x101090) > > +#define DG1_DMC_DEBUG3 _MMIO(0x13415c) > > > > /* Display Internal Timeout Register */ > > #define RM_TIMEOUT _MMIO(0x42060) > > -- > > 2.25.0.rc2 > > >=20 > -- > Matt Roper > Graphics Software Engineer > VTT-OSGC Platform Enablement > Intel Corporation > (916) 356-2795