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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BL1PR12MB5157.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3760e40d-b9cd-4eee-3f61-08da17d90a95 X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Apr 2022 14:23:37.7367 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 9byUndFM7RjUDrBWGrEF7utem/Zu0r8EzriyItVwpWVF82sdcf0NMByCrhdQI9RlCxZVnKueN2jR7hc6PJOm4A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1348 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org [Public] > > [Public] >=20 > Really useful information that your post is public while some of the > earlier posts in this _public_ thread were marked '[AMD confidential]'. AMD's mail system adds this tag. You'll see it in my next reply too. You might be referring to Lewis' earlier email that had "AMD Official Use O= nly". I don't believe anything has been tagged as confidential. >=20 > >> >> This seem _bit_ at odds with the commit message (and the AMD SSBD > >> >> whitepaper): > >> >> > >> >>> Add the necessary synchronization logic for AMD family 17H. > >> >> So, is X86_FEATURE_ZEN for family=3D=3D0x17, or family>=3D0x17? > >> > There are Zen family CPUs and APUs from family 0x19. Perhaps at the > >> > time of the whitepaper there weren't yet though. > >> > >> Is this a gap in the documentation, then? Is there some documentation > >> of the availability of SSBD mitigations on family 0x19? > > > > It looks like a misinterpretation of the document. >=20 > Not at all. The document does not mention family 19h at all. So where is > the misinterpretation? >=20 > Dave was asking for documentation for family 0x19, right? >=20 > > Notice it mentions in Non-architectural MSRs explicitly: > > > > "some models of family 17h have logic that allow loads to bypass older > stores > > but lack the architectural SPEC_CTRL or VIRT_SPEC_CTR" >=20 > That's relevant to Dave's question in which way? The document is proposing logic that includes saying that if the CPU suppor= ts the architectural MSR then use that. If it doesn't then do this other stuf= f. It specifically mentions that some CPUs in family 17h don't support the arc= hitectural MSR. The document is *not intended* to be comprehensive list of CPUs that suppor= t It. Documentation for individual CPUs indicate the availability of the MSR= . >=20 > > But that is not for all family 17h nor for family 19h. You can see ear= lier in > > the document the method to detect presence for SSBD which applies to > the > > rest of 17h and 19h. >=20 > We know how to read this document. But this document does not mention > anything else than family 17h. So what are you talking about? >=20 > > That code in amd_set_core_ssb_state is only used for one of the > > mitigation codepaths without MSR support, not for all Zen CPUs. >=20 > Again, how is that relevant to the legitimate question whether that > document applies to family 17h only or to 17h+ which includes 19h? To confirm the availability of the MSR for a particular CPU, you can look at the PPR for a family 19h CPU. For example here is family 19h model 01h: https://www.amd.com/en/support/tech-docs/processor-programming-reference-pp= r-for-amd-family-19h-model-01h-revision-b1?msclkid=3Df5047d01b5b211ec8d619d= 1385260e2d >=20 > We need to make a decison about what X86_FEATURE_ZEN means. Is it that > hard to give an authoritive answer? >=20 The comment currently associated with X86_FEATURE_ZEN is appropriate that i= t means family 17h or newer. There is an ask in this thread for clarifying t= hat comment it's for all CPUs with the Zen microarchitecture, and I believe that will b= e something that Wyes will do as a follow up.