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boundary="===============0884656507==" Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" --===============0884656507== Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_BL1PR12MB52247728007EA5D768476491FBEB9BL1PR12MB5224namp_" --_000_BL1PR12MB52247728007EA5D768476491FBEB9BL1PR12MB5224namp_ Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable [AMD Official Use Only] Reviewed-By: John Clements ________________________________ From: Joshi, Mukul Sent: Thursday, July 29, 2021 11:37 PM To: amd-gfx@lists.freedesktop.org Cc: Clements, John ; Zhang, Hawking ; Joshi, Mukul Subject: [PATCH] drm/amdgpu: Fix channel_index table layout for Aldebaran Fix the channel_index table layout to fetch the correct channel_index when calculating physical address from normalized address during page retirement. Also, fix the number of UMC instances and number of channels within each UMC instance for Aldebaran. Signed-off-by: Mukul Joshi --- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/umc_v6_7.c | 16 ++++++++-------- drivers/gpu/drm/amd/amdgpu/umc_v6_7.h | 4 ++-- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/am= dgpu/gmc_v9_0.c index 7cf653f9e9a7..097230b5e946 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -1171,8 +1171,8 @@ static void gmc_v9_0_set_umc_funcs(struct amdgpu_devi= ce *adev) break; case CHIP_ALDEBARAN: adev->umc.max_ras_err_cnt_per_query =3D UMC_V6_7_TOTAL_CHA= NNEL_NUM; - adev->umc.channel_inst_num =3D UMC_V6_7_UMC_INSTANCE_NUM; - adev->umc.umc_inst_num =3D UMC_V6_7_CHANNEL_INSTANCE_NUM; + adev->umc.channel_inst_num =3D UMC_V6_7_CHANNEL_INSTANCE_NU= M; + adev->umc.umc_inst_num =3D UMC_V6_7_UMC_INSTANCE_NUM; adev->umc.channel_offs =3D UMC_V6_7_PER_CHANNEL_OFFSET; if (!adev->gmc.xgmi.connected_to_cpu) adev->umc.ras_funcs =3D &umc_v6_7_ras_funcs; diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c b/drivers/gpu/drm/amd/am= dgpu/umc_v6_7.c index 7da12110425c..bb30336b1e8d 100644 --- a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c +++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c @@ -30,17 +30,17 @@ const uint32_t umc_v6_7_channel_idx_tbl_second[UMC_V6_7_UMC_INSTANCE_NUM][UMC_V6_= 7_CHANNEL_INSTANCE_NUM] =3D { - {28, 12, 6, 22}, {19, 3, 9, 25}, - {20, 4, 30, 14}, {11, 27, 1, 17}, - {24, 8, 2, 18}, {15, 31, 5, 21}, - {16, 0, 26, 10}, {7, 23, 29, 13} + {28, 20, 24, 16, 12, 4, 8, 0}, + {6, 30, 2, 26, 22, 14, 18, 10}, + {19, 11, 15, 7, 3, 27, 31, 23}, + {9, 1, 5, 29, 25, 17, 21, 13} }; const uint32_t umc_v6_7_channel_idx_tbl_first[UMC_V6_7_UMC_INSTANCE_NUM][UMC_V6_7= _CHANNEL_INSTANCE_NUM] =3D { - {19, 3, 9, 25}, {28, 12, 6, 22}, - {11, 27, 1, 17}, {20, 4, 30, 14}, - {15, 31, 5, 21}, {24, 8, 2, 18}, - {7, 23, 29, 13}, {16, 0, 26, 10} + {19, 11, 15, 7, 3, 27, 31, 23}, + {9, 1, 5, 29, 25, 17, 21, 13}, + {28, 20, 24, 16, 12, 4, 8, 0}, + {6, 30, 2, 26, 22, 14, 18, 10}, }; static inline uint32_t get_umc_v6_7_reg_offset(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.h b/drivers/gpu/drm/amd/am= dgpu/umc_v6_7.h index 81b8f1844091..57f2557e7aca 100644 --- a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.h +++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.h @@ -36,9 +36,9 @@ #define UMC_V6_7_INST_DIST 0x40000 /* number of umc channel instance with memory map register access */ -#define UMC_V6_7_CHANNEL_INSTANCE_NUM 4 +#define UMC_V6_7_UMC_INSTANCE_NUM 4 /* number of umc instance with memory map register access */ -#define UMC_V6_7_UMC_INSTANCE_NUM 8 +#define UMC_V6_7_CHANNEL_INSTANCE_NUM 8 /* total channel instances in one umc block */ #define UMC_V6_7_TOTAL_CHANNEL_NUM (UMC_V6_7_CHANNEL_INSTANCE_NUM * U= MC_V6_7_UMC_INSTANCE_NUM) /* UMC regiser per channel offset */ -- 2.17.1 --_000_BL1PR12MB52247728007EA5D768476491FBEB9BL1PR12MB5224namp_ Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable

[AMD Official Use Only]


Reviewed-By: John Clements <john.clements@amd.com>

From: Joshi, Mukul <Mu= kul.Joshi@amd.com>
Sent: Thursday, July 29, 2021 11:37 PM
To: amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org&= gt;
Cc: Clements, John <John.Clements@amd.com>; Zhang, Hawking <= ;Hawking.Zhang@amd.com>; Joshi, Mukul <Mukul.Joshi@amd.com>
Subject: [PATCH] drm/amdgpu: Fix channel_index table layout for Alde= baran
 
Fix the channel_index table layout to fetch the co= rrect
channel_index when calculating physical address from
normalized address during page retirement.
Also, fix the number of UMC instances and number of channels
within each UMC instance for Aldebaran.

Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c |  4 ++--
 drivers/gpu/drm/amd/amdgpu/umc_v6_7.c | 16 ++++++++--------
 drivers/gpu/drm/amd/amdgpu/umc_v6_7.h |  4 ++--
 3 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/am= dgpu/gmc_v9_0.c
index 7cf653f9e9a7..097230b5e946 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -1171,8 +1171,8 @@ static void gmc_v9_0_set_umc_funcs(struct amdgpu_devi= ce *adev)
            &nb= sp;    break;
         case CHIP_ALDEBARAN:
            &nb= sp;    adev->umc.max_ras_err_cnt_per_query =3D UMC_V6_7_T= OTAL_CHANNEL_NUM;
-            &n= bsp;  adev->umc.channel_inst_num =3D UMC_V6_7_UMC_INSTANCE_NUM;
-            &n= bsp;  adev->umc.umc_inst_num =3D UMC_V6_7_CHANNEL_INSTANCE_NUM;
+            &n= bsp;  adev->umc.channel_inst_num =3D UMC_V6_7_CHANNEL_INSTANCE_NUM;=
+            &n= bsp;  adev->umc.umc_inst_num =3D UMC_V6_7_UMC_INSTANCE_NUM;
            &nb= sp;    adev->umc.channel_offs =3D UMC_V6_7_PER_CHANNEL_OF= FSET;
            &nb= sp;    if (!adev->gmc.xgmi.connected_to_cpu)
            &nb= sp;            adev-= >umc.ras_funcs =3D &umc_v6_7_ras_funcs;
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c b/drivers/gpu/drm/amd/am= dgpu/umc_v6_7.c
index 7da12110425c..bb30336b1e8d 100644
--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
@@ -30,17 +30,17 @@
 
 const uint32_t
         umc_v6_7_channel_idx_tbl_s= econd[UMC_V6_7_UMC_INSTANCE_NUM][UMC_V6_7_CHANNEL_INSTANCE_NUM] =3D {
-            &n= bsp;  {28, 12, 6, 22},        {19, = 3, 9, 25},
-            &n= bsp;  {20, 4, 30, 14},        {11, = 27, 1, 17},
-            &n= bsp;  {24, 8, 2, 18},         = {15, 31, 5, 21},
-            &n= bsp;  {16, 0, 26, 10},        {7, 2= 3, 29, 13}
+            &n= bsp;  {28, 20, 24, 16, 12, 4, 8, 0},
+            &n= bsp;  {6, 30, 2, 26, 22, 14, 18, 10},
+            &n= bsp;  {19, 11, 15, 7, 3, 27, 31, 23},
+            &n= bsp;  {9, 1, 5, 29, 25, 17, 21, 13}
 };
 const uint32_t
         umc_v6_7_channel_idx_tbl_f= irst[UMC_V6_7_UMC_INSTANCE_NUM][UMC_V6_7_CHANNEL_INSTANCE_NUM] =3D {
-            &n= bsp;  {19, 3, 9, 25},         = {28, 12, 6, 22},
-            &n= bsp;  {11, 27, 1, 17},        {20, = 4, 30, 14},
-            &n= bsp;  {15, 31, 5, 21},        {24, = 8, 2, 18},
-            &n= bsp;  {7, 23, 29, 13},        {16, = 0, 26, 10}
+            &n= bsp;  {19, 11, 15, 7, 3, 27, 31, 23},
+            &n= bsp;  {9, 1, 5, 29, 25, 17, 21, 13},
+            &n= bsp;  {28, 20, 24, 16, 12, 4, 8, 0},
+            &n= bsp;  {6, 30, 2, 26, 22, 14, 18, 10},
 };
 
 static inline uint32_t get_umc_v6_7_reg_offset(struct amdgpu_device *= adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.h b/drivers/gpu/drm/amd/am= dgpu/umc_v6_7.h
index 81b8f1844091..57f2557e7aca 100644
--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.h
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.h
@@ -36,9 +36,9 @@
 #define UMC_V6_7_INST_DIST      0x40000
 
 /* number of umc channel instance with memory map register access */<= br> -#define UMC_V6_7_CHANNEL_INSTANCE_NUM      &= nbsp;   4
+#define UMC_V6_7_UMC_INSTANCE_NUM       = ;       4
 /* number of umc instance with memory map register access */
-#define UMC_V6_7_UMC_INSTANCE_NUM       = ;       8
+#define UMC_V6_7_CHANNEL_INSTANCE_NUM      &= nbsp;   8
 /* total channel instances in one umc block */
 #define UMC_V6_7_TOTAL_CHANNEL_NUM      (UMC= _V6_7_CHANNEL_INSTANCE_NUM * UMC_V6_7_UMC_INSTANCE_NUM)
 /* UMC regiser per channel offset */
--
2.17.1

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