[U-Boot] [PATCH v7 3/7] mips: ath79: add support for QCA953x SOCs

[Wills Wang <wills.wang@live.com>]

On Sunday, January 17, 2016 03:33 AM, Marek Vasut wrote:
> On Saturday, January 16, 2016 at 07:13:49 PM, Wills Wang wrote:
>> This patch enable work for qca953x SOC.
>>
>> Signed-off-by: Wills Wang <wills.wang@live.com>
>> ---
>>
>> Changes in v7:
>> - Use CKSEGxADDR instead of KSEGxADDR for qca953x
>>
>> Changes in v6: None
>> Changes in v5: None
>> Changes in v4: None
>> Changes in v3: None
>> Changes in v2: None
> [...]
>
>> +int get_serial_clock(void)
>> +{
>> +	return qca953x_get_xtal();
>> +}
>> +
>> +int get_clocks(void)
>> +{
>> +	void __iomem *regs;
>> +	u32 val, ctrl, xtal, pll, div;
> This looks like a copy of the same code in patch 2/7 .
There are different in detail.
>> +	regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
>> +			   MAP_NOCACHE);
>> +
>> +	xtal = qca953x_get_xtal();
>> +	ctrl = readl(regs + QCA953X_PLL_CLK_CTRL_REG);
>> +	val = readl(regs + QCA953X_PLL_CPU_CONFIG_REG);
> [...]
>
>> +void ddr_init(void)
>> +{
>> +	void __iomem *regs;
>> +	u32 val;
> This looks like a copy of the same code in patch 2/7 .
>
There are different in detail, the bit fields of register are not identical
copies of one another. there is no way to extract a common code.
>> +	regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
>> +			   MAP_NOCACHE);
>> +	val = get_bootstrap();
>> +	if (val & QCA953X_BOOTSTRAP_DDR1) {
>> +		writel(DDR_CTL_CONFIG_VAL, regs + QCA953X_DDR_REG_CTL_CONF);
>> +		udelay(10);
>> +
>> +		/* For 16-bit DDR */
>> +		writel(0xffff, regs + AR71XX_DDR_REG_RD_CYCLE);
>> +		udelay(100);
>> +
>> +		/* Burst size */
>> +		writel(DDR_BURST_VAL, regs + QCA953X_DDR_REG_BURST);
>> +		udelay(100);
>> +		writel(DDR_BURST2_VAL, regs + QCA953X_DDR_REG_BURST2);
>> +		udelay(100);
>> +
>> +		/* AHB maximum timeout */
>> +		writel(0xfffff, regs + QCA953X_DDR_REG_TIMEOUT_MAX);
>> +		udelay(100);
>> +
>> +		/* DRAM timing */
>> +		writel(DDR1_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG);
>> +		udelay(100);
>> +		writel(DDR1_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2);
>> +		udelay(100);
>> +		writel(DDR1_CONF3_REG_VAL, regs + QCA953X_DDR_REG_CONFIG3);
>> +		udelay(100);
> [...]

-- 
Best Regards
Wills