From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [RFC,5/6] dmaengine: xilinx_dma: Program interrupt delay timeout From: Radhey Shyam Pandey Message-Id: Date: Tue, 17 Apr 2018 12:48:14 +0000 To: Vinod Koul Cc: "dan.j.williams@intel.com" , "michal.simek@xilinx.com" , Appana Durga Kedareswara Rao , "lars@metafoo.de" , "dmaengine@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "'RADHEYCS@GMAIL.COM'" List-ID: SGkgVmlub2QsCgo+IC0tLS0tT3JpZ2luYWwgTWVzc2FnZS0tLS0tCj4gRnJvbTogVmlub2QgS291 bCBbbWFpbHRvOnZpbm9kLmtvdWxAaW50ZWwuY29tXQo+IFNlbnQ6IFdlZG5lc2RheSwgQXByaWwg MTEsIDIwMTggMjo0MiBQTQo+IFRvOiBSYWRoZXkgU2h5YW0gUGFuZGV5IDxyYWRoZXlzQHhpbGlu eC5jb20+Cj4gQ2M6IGRhbi5qLndpbGxpYW1zQGludGVsLmNvbTsgbWljaGFsLnNpbWVrQHhpbGlu eC5jb207IEFwcGFuYSBEdXJnYQo+IEtlZGFyZXN3YXJhIFJhbyA8YXBwYW5hZEB4aWxpbnguY29t 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aW54X2RtYV9jb21wbGV0ZV9kZXNjcmlwdG9yKGNoYW4pOwo+ID4gIAkJY2hhbi0+aWRsZSA9IHRy dWU7Cj4gPiAtLQo+ID4gMS43LjEKPiA+Cj4gCj4gLS0KPiB+Vmlub2QKLS0tClRvIHVuc3Vic2Ny aWJlIGZyb20gdGhpcyBsaXN0OiBzZW5kIHRoZSBsaW5lICJ1bnN1YnNjcmliZSBkbWFlbmdpbmUi IGluCnRoZSBib2R5IG9mIGEgbWVzc2FnZSB0byBtYWpvcmRvbW9Admdlci5rZXJuZWwub3JnCk1v cmUgbWFqb3Jkb21vIGluZm8gYXQgIGh0dHA6Ly92Z2VyLmtlcm5lbC5vcmcvbWFqb3Jkb21vLWlu Zm8uaHRtbAo= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753314AbeDQMsT (ORCPT ); Tue, 17 Apr 2018 08:48:19 -0400 Received: from mail-sn1nam02on0054.outbound.protection.outlook.com ([104.47.36.54]:33180 "EHLO NAM02-SN1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752796AbeDQMsR (ORCPT ); Tue, 17 Apr 2018 08:48:17 -0400 From: Radhey Shyam Pandey To: Vinod Koul CC: "dan.j.williams@intel.com" , "michal.simek@xilinx.com" , "Appana Durga Kedareswara Rao" , "lars@metafoo.de" , "dmaengine@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "'RADHEYCS@GMAIL.COM'" Subject: RE: [RFC 5/6] dmaengine: xilinx_dma: Program interrupt delay timeout Thread-Topic: [RFC 5/6] dmaengine: xilinx_dma: Program interrupt delay timeout Thread-Index: AQHTym7m/FvHP37H0EyBh1KYjLHUhaP7VWyAgAmlbQA= Date: Tue, 17 Apr 2018 12:48:14 +0000 Message-ID: References: <1522665546-10035-1-git-send-email-radheys@xilinx.com> <1522665546-10035-6-git-send-email-radheys@xilinx.com> <20180411091159.GA6014@localhost> In-Reply-To: <20180411091159.GA6014@localhost> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=radheys@xilinx.com; x-originating-ip: [182.72.145.30] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 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X-MS-Office365-Filtering-Correlation-Id: d40c657b-c2dd-45c1-5d22-08d5a4617c42 X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-Network-Message-Id: d40c657b-c2dd-45c1-5d22-08d5a4617c42 X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Apr 2018 12:48:14.5675 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR02MB2324 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by mail.home.local id w3HCmNPl015514 Hi Vinod, > -----Original Message----- > From: Vinod Koul [mailto:vinod.koul@intel.com] > Sent: Wednesday, April 11, 2018 2:42 PM > To: Radhey Shyam Pandey > Cc: dan.j.williams@intel.com; michal.simek@xilinx.com; Appana Durga > Kedareswara Rao ; Radhey Shyam Pandey > ; lars@metafoo.de; dmaengine@vger.kernel.org; > linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org > Subject: Re: [RFC 5/6] dmaengine: xilinx_dma: Program interrupt delay > timeout > > On Mon, Apr 02, 2018 at 04:09:05PM +0530, Radhey Shyam Pandey wrote: > > Program IRQDelay for AXI DMA. The interrupt timeout mechanism causes > > the DMA engine to generate an interrupt after the delay time period > > has expired. It enables dmaengine to respond in real-time even though > > interrupt coalescing is configured. > > again you are doing this only for axieth_connected, why is that? The initial application was axieth but yes delay timeout feature may be needed for other use cases as well. We can make delay timeout an optional DT property. Is that fine? > > > > > Signed-off-by: Radhey Shyam Pandey > > --- > > drivers/dma/xilinx/xilinx_dma.c | 16 ++++++++++++++-- > > 1 files changed, 14 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/dma/xilinx/xilinx_dma.c > b/drivers/dma/xilinx/xilinx_dma.c > > index 518465e..ab8f1b0 100644 > > --- a/drivers/dma/xilinx/xilinx_dma.c > > +++ b/drivers/dma/xilinx/xilinx_dma.c > > @@ -161,8 +161,12 @@ > > /* AXI DMA Specific Masks/Bit fields */ > > #define XILINX_DMA_MAX_TRANS_LEN GENMASK(22, 0) > > #define XILINX_DMA_CR_COALESCE_MAX GENMASK(23, 16) > > +#define XILINX_DMA_CR_DELAY_MAX GENMASK(31, 24) > > #define XILINX_DMA_CR_CYCLIC_BD_EN_MASK BIT(4) > > #define XILINX_DMA_CR_COALESCE_SHIFT 16 > > +#define XILINX_DMA_CR_DELAY_SHIFT 24 > > +#define XILINX_DMA_CR_WAITBOUND_DFT 254 > > + > > #define XILINX_DMA_BD_SOP BIT(27) > > #define XILINX_DMA_BD_EOP BIT(26) > > #define XILINX_DMA_COALESCE_MAX 255 > > @@ -1294,6 +1298,12 @@ static void xilinx_dma_start_transfer(struct > xilinx_dma_chan *chan) > > reg &= ~XILINX_DMA_CR_COALESCE_MAX; > > reg |= chan->desc_pendingcount << > > XILINX_DMA_CR_COALESCE_SHIFT; > > + > > + if (chan->xdev->has_axieth_connected) { > > + reg &= ~XILINX_DMA_CR_DELAY_MAX; > > + reg |= XILINX_DMA_CR_WAITBOUND_DFT << > > + XILINX_DMA_CR_DELAY_SHIFT; > > + } > > dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); > > } > > > > @@ -1508,7 +1518,8 @@ static irqreturn_t xilinx_dma_irq_handler(int irq, > void *data) > > } > > } > > > > - if (status & XILINX_DMA_DMASR_DLY_CNT_IRQ) { > > + if (!chan->xdev->has_axieth_connected && (status & > > + XILINX_DMA_DMASR_DLY_CNT_IRQ)) { > > /* > > * Device takes too long to do the transfer when user > requires > > * responsiveness. > > @@ -1516,7 +1527,8 @@ static irqreturn_t xilinx_dma_irq_handler(int irq, > void *data) > > dev_dbg(chan->dev, "Inter-packet latency too long\n"); > > } > > > > - if (status & XILINX_DMA_DMASR_FRM_CNT_IRQ) { > > + if (status & (XILINX_DMA_DMASR_FRM_CNT_IRQ | > > + XILINX_DMA_DMASR_DLY_CNT_IRQ)) { > > spin_lock(&chan->lock); > > xilinx_dma_complete_descriptor(chan); > > chan->idle = true; > > -- > > 1.7.1 > > > > -- > ~Vinod From mboxrd@z Thu Jan 1 00:00:00 1970 From: radheys@xilinx.com (Radhey Shyam Pandey) Date: Tue, 17 Apr 2018 12:48:14 +0000 Subject: [RFC 5/6] dmaengine: xilinx_dma: Program interrupt delay timeout In-Reply-To: <20180411091159.GA6014@localhost> References: <1522665546-10035-1-git-send-email-radheys@xilinx.com> <1522665546-10035-6-git-send-email-radheys@xilinx.com> <20180411091159.GA6014@localhost> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi Vinod, > -----Original Message----- > From: Vinod Koul [mailto:vinod.koul at intel.com] > Sent: Wednesday, April 11, 2018 2:42 PM > To: Radhey Shyam Pandey > Cc: dan.j.williams at intel.com; michal.simek at xilinx.com; Appana Durga > Kedareswara Rao ; Radhey Shyam Pandey > ; lars at metafoo.de; dmaengine at vger.kernel.org; > linux-arm-kernel at lists.infradead.org; linux-kernel at vger.kernel.org > Subject: Re: [RFC 5/6] dmaengine: xilinx_dma: Program interrupt delay > timeout > > On Mon, Apr 02, 2018 at 04:09:05PM +0530, Radhey Shyam Pandey wrote: > > Program IRQDelay for AXI DMA. The interrupt timeout mechanism causes > > the DMA engine to generate an interrupt after the delay time period > > has expired. It enables dmaengine to respond in real-time even though > > interrupt coalescing is configured. > > again you are doing this only for axieth_connected, why is that? The initial application was axieth but yes delay timeout feature may be needed for other use cases as well. We can make delay timeout an optional DT property. Is that fine? > > > > > Signed-off-by: Radhey Shyam Pandey > > --- > > drivers/dma/xilinx/xilinx_dma.c | 16 ++++++++++++++-- > > 1 files changed, 14 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/dma/xilinx/xilinx_dma.c > b/drivers/dma/xilinx/xilinx_dma.c > > index 518465e..ab8f1b0 100644 > > --- a/drivers/dma/xilinx/xilinx_dma.c > > +++ b/drivers/dma/xilinx/xilinx_dma.c > > @@ -161,8 +161,12 @@ > > /* AXI DMA Specific Masks/Bit fields */ > > #define XILINX_DMA_MAX_TRANS_LEN GENMASK(22, 0) > > #define XILINX_DMA_CR_COALESCE_MAX GENMASK(23, 16) > > +#define XILINX_DMA_CR_DELAY_MAX GENMASK(31, 24) > > #define XILINX_DMA_CR_CYCLIC_BD_EN_MASK BIT(4) > > #define XILINX_DMA_CR_COALESCE_SHIFT 16 > > +#define XILINX_DMA_CR_DELAY_SHIFT 24 > > +#define XILINX_DMA_CR_WAITBOUND_DFT 254 > > + > > #define XILINX_DMA_BD_SOP BIT(27) > > #define XILINX_DMA_BD_EOP BIT(26) > > #define XILINX_DMA_COALESCE_MAX 255 > > @@ -1294,6 +1298,12 @@ static void xilinx_dma_start_transfer(struct > xilinx_dma_chan *chan) > > reg &= ~XILINX_DMA_CR_COALESCE_MAX; > > reg |= chan->desc_pendingcount << > > XILINX_DMA_CR_COALESCE_SHIFT; > > + > > + if (chan->xdev->has_axieth_connected) { > > + reg &= ~XILINX_DMA_CR_DELAY_MAX; > > + reg |= XILINX_DMA_CR_WAITBOUND_DFT << > > + XILINX_DMA_CR_DELAY_SHIFT; > > + } > > dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); > > } > > > > @@ -1508,7 +1518,8 @@ static irqreturn_t xilinx_dma_irq_handler(int irq, > void *data) > > } > > } > > > > - if (status & XILINX_DMA_DMASR_DLY_CNT_IRQ) { > > + if (!chan->xdev->has_axieth_connected && (status & > > + XILINX_DMA_DMASR_DLY_CNT_IRQ)) { > > /* > > * Device takes too long to do the transfer when user > requires > > * responsiveness. > > @@ -1516,7 +1527,8 @@ static irqreturn_t xilinx_dma_irq_handler(int irq, > void *data) > > dev_dbg(chan->dev, "Inter-packet latency too long\n"); > > } > > > > - if (status & XILINX_DMA_DMASR_FRM_CNT_IRQ) { > > + if (status & (XILINX_DMA_DMASR_FRM_CNT_IRQ | > > + XILINX_DMA_DMASR_DLY_CNT_IRQ)) { > > spin_lock(&chan->lock); > > xilinx_dma_complete_descriptor(chan); > > chan->idle = true; > > -- > > 1.7.1 > > > > -- > ~Vinod