* [PATCH] drm/amdgpu/display: fix logic regression in dce110 apply_single_controller_ctx_to_hw
@ 2021-08-25 17:06 Alex Deucher
2021-08-25 21:01 ` Zuo, Jerry
0 siblings, 1 reply; 2+ messages in thread
From: Alex Deucher @ 2021-08-25 17:06 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Fangzhi Zuo
Commit 5de27e1d6755 ("drm/amd/display: Add DP 2.0 SST DC Support")
added a new check for DP 2.0 with a CONFIG_DRM_AMD_DC_DCN check
that removed a bunch of logic if CONFIG_DRM_AMD_DC_DCN was not set,
restore that logic.
Fixes: 5de27e1d6755 ("drm/amd/display: Add DP 2.0 SST DC Support")
Cc: Fangzhi Zuo <Jerry.Zuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
.../gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 7 +------
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 33743dc2631c..f660472e71fb 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1545,6 +1545,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(
* function core_link_enable_stream
*/
if (!(hws->wa.dp_hpo_and_otg_sequence && is_dp_128b_132b_signal(pipe_ctx)))
+#endif
/* */
/* Do not touch stream timing on seamless boot optimization. */
if (!pipe_ctx->stream->apply_seamless_boot_optimization)
@@ -1558,12 +1559,6 @@ static enum dc_status apply_single_controller_ctx_to_hw(
if (pipe_ctx->stream_res.tg->funcs->set_drr)
pipe_ctx->stream_res.tg->funcs->set_drr(
pipe_ctx->stream_res.tg, ¶ms);
-#else
- /* */
- /* Do not touch stream timing on seamless boot optimization. */
- if (!pipe_ctx->stream->apply_seamless_boot_optimization)
- hws->funcs.enable_stream_timing(pipe_ctx, context, dc);
-#endif
// DRR should set trigger event to monitor surface update event
if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0)
--
2.31.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* RE: [PATCH] drm/amdgpu/display: fix logic regression in dce110 apply_single_controller_ctx_to_hw
2021-08-25 17:06 [PATCH] drm/amdgpu/display: fix logic regression in dce110 apply_single_controller_ctx_to_hw Alex Deucher
@ 2021-08-25 21:01 ` Zuo, Jerry
0 siblings, 0 replies; 2+ messages in thread
From: Zuo, Jerry @ 2021-08-25 21:01 UTC (permalink / raw)
To: Deucher, Alexander, amd-gfx
[AMD Official Use Only]
Thanks for pointing out the mistake.
Reviewed-by: Fangzhi Zuo <Jerry.Zuo@amd.com>
-----Original Message-----
From: Deucher, Alexander <Alexander.Deucher@amd.com>
Sent: August 25, 2021 1:07 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Zuo, Jerry <Jerry.Zuo@amd.com>
Subject: [PATCH] drm/amdgpu/display: fix logic regression in dce110 apply_single_controller_ctx_to_hw
Commit 5de27e1d6755 ("drm/amd/display: Add DP 2.0 SST DC Support") added a new check for DP 2.0 with a CONFIG_DRM_AMD_DC_DCN check that removed a bunch of logic if CONFIG_DRM_AMD_DC_DCN was not set, restore that logic.
Fixes: 5de27e1d6755 ("drm/amd/display: Add DP 2.0 SST DC Support")
Cc: Fangzhi Zuo <Jerry.Zuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
.../gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 7 +------
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 33743dc2631c..f660472e71fb 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1545,6 +1545,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(
* function core_link_enable_stream
*/
if (!(hws->wa.dp_hpo_and_otg_sequence && is_dp_128b_132b_signal(pipe_ctx)))
+#endif
/* */
/* Do not touch stream timing on seamless boot optimization. */
if (!pipe_ctx->stream->apply_seamless_boot_optimization)
@@ -1558,12 +1559,6 @@ static enum dc_status apply_single_controller_ctx_to_hw(
if (pipe_ctx->stream_res.tg->funcs->set_drr)
pipe_ctx->stream_res.tg->funcs->set_drr(
pipe_ctx->stream_res.tg, ¶ms);
-#else
- /* */
- /* Do not touch stream timing on seamless boot optimization. */
- if (!pipe_ctx->stream->apply_seamless_boot_optimization)
- hws->funcs.enable_stream_timing(pipe_ctx, context, dc);
-#endif
// DRR should set trigger event to monitor surface update event
if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0)
--
2.31.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
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2021-08-25 21:01 ` Zuo, Jerry
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