From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-dm3nam03on0063.outbound.protection.outlook.com ([104.47.41.63]:33568 "EHLO NAM03-DM3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751262AbdCBSeK (ORCPT ); Thu, 2 Mar 2017 13:34:10 -0500 From: "Deucher, Alexander" To: 'Jean Delvare' , "stable@vger.kernel.org" CC: "Cui, Flora" , "Zhang, Jerry" Subject: RE: [PATCH] Revert "drm/amdgpu: update tile table for oland/hainan" Date: Thu, 2 Mar 2017 17:58:14 +0000 Message-ID: References: <20170302182135.3afe11e1@endymion> In-Reply-To: <20170302182135.3afe11e1@endymion> Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org List-ID: > -----Original Message----- > From: Jean Delvare [mailto:jdelvare@suse.de] > Sent: Thursday, March 02, 2017 12:22 PM > To: stable@vger.kernel.org > Cc: Cui, Flora; Zhang, Jerry; Deucher, Alexander > Subject: [PATCH] Revert "drm/amdgpu: update tile table for oland/hainan" >=20 > Revert commit f8d9422ef80c ("drm/amdgpu: update tile table for > oland/hainan") as it is causing ugly visual artifacts on at least > Oland. This is only an optimization so we can live without it. >=20 > This fixes kernel bug #194761: > amdgpu driver breaks on Oland (SI) > https://bugzilla.kernel.org/show_bug.cgi?id=3D194761 >=20 > Signed-off-by: Jean Delvare > Fixes: f8d9422ef80c ("drm/amdgpu: update tile table for oland/hainan") > Cc: Flora Cui > Cc: Junwei Zhang > Cc: Alex Deucher Acked-by: Alex Deucher > --- > Note: This is for stable v4.10 branch only. v4.11 and later have a > different fix, but it's much larger and more intrusive so not suitable > for a stable branch. >=20 > drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 330 ++++++++++++++---------- > ---------- > 1 file changed, 139 insertions(+), 191 deletions(-) >=20 > --- linux-4.10.orig/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 2017-02-19 > 23:34:00.000000000 +0100 > +++ linux-4.10/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 2017-03-02 > 18:10:45.786414946 +0100 > @@ -708,290 +708,238 @@ static void gfx_v6_0_tiling_mode_table_i > for (reg_offset =3D 0; reg_offset < num_tile_mode_states; > reg_offset++) { > switch (reg_offset) { > case 0: > - gb_tile_moden =3D > (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | > - > ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > - > PIPE_CONFIG(ADDR_SURF_P2) | > + gb_tile_moden =3D > (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > + > MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | > + > PIPE_CONFIG(ADDR_SURF_P4_8x16) | >=20 > TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | > + > NUM_BANKS(ADDR_SURF_16_BANK) | >=20 > BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | >=20 > BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | > - > MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | > - > NUM_BANKS(ADDR_SURF_16_BANK)); > + > MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); > break; > case 1: > - gb_tile_moden =3D > (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | > - > ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > - > PIPE_CONFIG(ADDR_SURF_P2) | > + gb_tile_moden =3D > (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > + > MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | > + > PIPE_CONFIG(ADDR_SURF_P4_8x16) | >=20 > TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | > + > NUM_BANKS(ADDR_SURF_16_BANK) | >=20 > BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | >=20 > BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | > - > MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | > - > NUM_BANKS(ADDR_SURF_16_BANK)); > + > MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); > break; > case 2: > - gb_tile_moden =3D > (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | > - > ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > - > PIPE_CONFIG(ADDR_SURF_P2) | > + gb_tile_moden =3D > (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > + > MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | > + > PIPE_CONFIG(ADDR_SURF_P4_8x16) | >=20 > TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | > + > NUM_BANKS(ADDR_SURF_16_BANK) | >=20 > BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | >=20 > BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | > - > MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | > - > NUM_BANKS(ADDR_SURF_16_BANK)); > + > MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); > break; > case 3: > - gb_tile_moden =3D > (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | > - > ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > - > PIPE_CONFIG(ADDR_SURF_P2) | > + gb_tile_moden =3D > (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > + > MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | > + > PIPE_CONFIG(ADDR_SURF_P4_8x16) | > + > TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | > + > NUM_BANKS(ADDR_SURF_16_BANK) | >=20 > BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | > - > BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | > - > MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | > - > NUM_BANKS(ADDR_SURF_8_BANK) | > - > TILE_SPLIT(split_equal_to_row_size)); > + > BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | > + > MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); > break; > case 4: > - gb_tile_moden =3D > (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | > - > ARRAY_MODE(ARRAY_1D_TILED_THIN1) | > - > PIPE_CONFIG(ADDR_SURF_P2)); > + gb_tile_moden =3D > (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | > + > MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | > + > PIPE_CONFIG(ADDR_SURF_P4_8x16) | > + > TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | > + > NUM_BANKS(ADDR_SURF_16_BANK) | > + > BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | > + > BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | > + > MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); > break; > case 5: > - gb_tile_moden =3D > (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | > - > ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > - > PIPE_CONFIG(ADDR_SURF_P2) | > - > TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | > + gb_tile_moden =3D > (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > + > MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | > + > PIPE_CONFIG(ADDR_SURF_P4_8x16) | > + > TILE_SPLIT(split_equal_to_row_size) | > + > NUM_BANKS(ADDR_SURF_16_BANK) | >=20 > BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | > - > BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | > - > MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | > - > NUM_BANKS(ADDR_SURF_8_BANK)); > + > BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | > + > MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); > break; > case 6: > - gb_tile_moden =3D > (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | > - > ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > - > PIPE_CONFIG(ADDR_SURF_P2) | > - > TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | > + gb_tile_moden =3D > (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > + > MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | > + > PIPE_CONFIG(ADDR_SURF_P4_8x16) | > + > TILE_SPLIT(split_equal_to_row_size) | > + > NUM_BANKS(ADDR_SURF_16_BANK) | >=20 > BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | > - > BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | > - > MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | > - > NUM_BANKS(ADDR_SURF_8_BANK)); > + > BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | > + > MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); > break; > case 7: > - gb_tile_moden =3D > (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | > - > ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > - > PIPE_CONFIG(ADDR_SURF_P2) | > - > TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | > + gb_tile_moden =3D > (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > + > MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | > + > PIPE_CONFIG(ADDR_SURF_P4_8x16) | > + > TILE_SPLIT(split_equal_to_row_size) | > + > NUM_BANKS(ADDR_SURF_16_BANK) | >=20 > BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | > - > BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | > - > MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | > - > NUM_BANKS(ADDR_SURF_4_BANK)); > + > BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | > + > MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); > break; > case 8: > - gb_tile_moden =3D > (ARRAY_MODE(ARRAY_LINEAR_ALIGNED)); > + gb_tile_moden =3D > (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | > + > MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | > + > PIPE_CONFIG(ADDR_SURF_P4_8x16) | > + > TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | > + > NUM_BANKS(ADDR_SURF_16_BANK) | > + > BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | > + > BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | > + > MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); > break; > case 9: > - gb_tile_moden =3D > (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | > - > ARRAY_MODE(ARRAY_1D_TILED_THIN1) | > - > PIPE_CONFIG(ADDR_SURF_P2)); > + gb_tile_moden =3D > (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | > + > MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | > + > PIPE_CONFIG(ADDR_SURF_P4_8x16) | > + > TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | > + > NUM_BANKS(ADDR_SURF_16_BANK) | > + > BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | > + > BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | > + > MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); > break; > case 10: > - gb_tile_moden =3D > (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | > - > ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > - > PIPE_CONFIG(ADDR_SURF_P2) | > + gb_tile_moden =3D > (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > + > MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | > + > PIPE_CONFIG(ADDR_SURF_P4_8x16) | >=20 > TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | > + > NUM_BANKS(ADDR_SURF_16_BANK) | >=20 > BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | >=20 > BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | > - > MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | > - > NUM_BANKS(ADDR_SURF_16_BANK)); > + > MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); > break; > case 11: > - gb_tile_moden =3D > (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | > - > ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > - > PIPE_CONFIG(ADDR_SURF_P2) | > + gb_tile_moden =3D > (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > + > MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | > + > PIPE_CONFIG(ADDR_SURF_P4_8x16) | >=20 > TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | > + > NUM_BANKS(ADDR_SURF_16_BANK) | >=20 > BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | >=20 > BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | > - > MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | > - > NUM_BANKS(ADDR_SURF_16_BANK)); > + > MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); > break; > case 12: > - gb_tile_moden =3D > (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | > - > ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > - > PIPE_CONFIG(ADDR_SURF_P2) | > + gb_tile_moden =3D > (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > + > MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | > + > PIPE_CONFIG(ADDR_SURF_P4_8x16) | >=20 > TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | > + > NUM_BANKS(ADDR_SURF_16_BANK) | >=20 > BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | >=20 > BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | > - > MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | > - > NUM_BANKS(ADDR_SURF_16_BANK)); > + > MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); > break; > case 13: > - gb_tile_moden =3D > (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | > - > ARRAY_MODE(ARRAY_1D_TILED_THIN1) | > - > PIPE_CONFIG(ADDR_SURF_P2)); > + gb_tile_moden =3D > (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | > + > MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | > + > PIPE_CONFIG(ADDR_SURF_P4_8x16) | > + > TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | > + > NUM_BANKS(ADDR_SURF_16_BANK) | > + > BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | > + > BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | > + > MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); > break; > case 14: > - gb_tile_moden =3D > (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | > - > ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > - > PIPE_CONFIG(ADDR_SURF_P2) | > + gb_tile_moden =3D > (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > + > MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | > + > PIPE_CONFIG(ADDR_SURF_P4_8x16) | >=20 > TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | > + > NUM_BANKS(ADDR_SURF_16_BANK) | >=20 > BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | >=20 > BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | > - > MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | > - > NUM_BANKS(ADDR_SURF_16_BANK)); > + > MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); > break; > case 15: > - gb_tile_moden =3D > (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | > - > ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > - > PIPE_CONFIG(ADDR_SURF_P2) | > + gb_tile_moden =3D > (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > + > MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | > + > PIPE_CONFIG(ADDR_SURF_P4_8x16) | >=20 > TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | > + > NUM_BANKS(ADDR_SURF_16_BANK) | >=20 > BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | >=20 > BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | > - > MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | > - > NUM_BANKS(ADDR_SURF_16_BANK)); > + > MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); > break; > case 16: > - gb_tile_moden =3D > (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | > - > ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > - > PIPE_CONFIG(ADDR_SURF_P2) | > + gb_tile_moden =3D > (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > + > MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | > + > PIPE_CONFIG(ADDR_SURF_P4_8x16) | >=20 > TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | > + > NUM_BANKS(ADDR_SURF_16_BANK) | >=20 > BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | >=20 > BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | > - > MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | > - > NUM_BANKS(ADDR_SURF_16_BANK)); > + > MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); > break; > case 17: > - gb_tile_moden =3D > (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | > - > ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > - > PIPE_CONFIG(ADDR_SURF_P2) | > - > BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | > - > BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | > - > MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | > - > NUM_BANKS(ADDR_SURF_16_BANK) | > - > TILE_SPLIT(split_equal_to_row_size)); > - break; > - case 18: > - gb_tile_moden =3D > (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | > - > ARRAY_MODE(ARRAY_1D_TILED_THICK) | > - > PIPE_CONFIG(ADDR_SURF_P2)); > - break; > - case 19: > - gb_tile_moden =3D > (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | > - > ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | > - > PIPE_CONFIG(ADDR_SURF_P2) | > - > BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | > - > BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | > - > MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | > + gb_tile_moden =3D > (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > + > MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | > + > PIPE_CONFIG(ADDR_SURF_P4_8x16) | > + > TILE_SPLIT(split_equal_to_row_size) | >=20 > NUM_BANKS(ADDR_SURF_16_BANK) | > - > TILE_SPLIT(split_equal_to_row_size)); > - break; > - case 20: > - gb_tile_moden =3D > (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | > - > ARRAY_MODE(ARRAY_2D_TILED_THICK) | > - > PIPE_CONFIG(ADDR_SURF_P2) | >=20 > BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | >=20 > BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | > - > MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | > - > NUM_BANKS(ADDR_SURF_16_BANK) | > - > TILE_SPLIT(split_equal_to_row_size)); > + > MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); > break; > case 21: > - gb_tile_moden =3D > (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | > - > ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > - > PIPE_CONFIG(ADDR_SURF_P2) | > + gb_tile_moden =3D > (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > + > MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | > + > PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | >=20 > TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | > + > NUM_BANKS(ADDR_SURF_16_BANK) | >=20 > BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | >=20 > BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | > - > MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | > - > NUM_BANKS(ADDR_SURF_8_BANK)); > + > MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); > break; > case 22: > - gb_tile_moden =3D > (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | > - > ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > - > PIPE_CONFIG(ADDR_SURF_P2) | > + gb_tile_moden =3D > (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > + > MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | > + > PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | >=20 > TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | > - > BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | > - > BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | > - > MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | > - > NUM_BANKS(ADDR_SURF_8_BANK)); > + > NUM_BANKS(ADDR_SURF_16_BANK) | > + > BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | > + > BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | > + > MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); > break; > case 23: > - gb_tile_moden =3D > (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | > - > ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > - > PIPE_CONFIG(ADDR_SURF_P2) | > + gb_tile_moden =3D > (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > + > MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | > + > PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | >=20 > TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | > + > NUM_BANKS(ADDR_SURF_16_BANK) | >=20 > BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | >=20 > BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | > - > MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | > - > NUM_BANKS(ADDR_SURF_8_BANK)); > + > MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); > break; > case 24: > - gb_tile_moden =3D > (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | > - > ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > - > PIPE_CONFIG(ADDR_SURF_P2) | > + gb_tile_moden =3D > (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > + > MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | > + > PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | >=20 > TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | > + > NUM_BANKS(ADDR_SURF_16_BANK) | >=20 > BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | >=20 > BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | > - > MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | > - > NUM_BANKS(ADDR_SURF_8_BANK)); > + > MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); > break; > case 25: > - gb_tile_moden =3D > (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | > - > ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > - > PIPE_CONFIG(ADDR_SURF_P2) | > + gb_tile_moden =3D > (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > + > MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | > + > PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | >=20 > TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | > - > BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | > - > BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | > - > MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | > - > NUM_BANKS(ADDR_SURF_4_BANK)); > - break; > - case 26: > - gb_tile_moden =3D > (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | > - > ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > - > PIPE_CONFIG(ADDR_SURF_P2) | > - > TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | > - > BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | > - > BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | > - > MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | > - > NUM_BANKS(ADDR_SURF_4_BANK)); > - break; > - case 27: > - gb_tile_moden =3D > (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | > - > ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > - > PIPE_CONFIG(ADDR_SURF_P2) | > - > TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | > - > BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | > - > BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | > - > MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | > - > NUM_BANKS(ADDR_SURF_4_BANK)); > - break; > - case 28: > - gb_tile_moden =3D > (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | > - > ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > - > PIPE_CONFIG(ADDR_SURF_P2) | > - > TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | > - > BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | > - > BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | > - > MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | > - > NUM_BANKS(ADDR_SURF_4_BANK)); > - break; > - case 29: > - gb_tile_moden =3D > (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | > - > ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > - > PIPE_CONFIG(ADDR_SURF_P2) | > - > TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | > - > BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | > - > BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | > - > MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | > - > NUM_BANKS(ADDR_SURF_4_BANK)); > - break; > - case 30: > - gb_tile_moden =3D > (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | > - > ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > - > PIPE_CONFIG(ADDR_SURF_P2) | > - > TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | > + > NUM_BANKS(ADDR_SURF_8_BANK) | >=20 > BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | >=20 > BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | > - > MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | > - > NUM_BANKS(ADDR_SURF_4_BANK)); > + > MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); > break; > default: > - continue; > + gb_tile_moden =3D 0; > + break; > } > adev->gfx.config.tile_mode_array[reg_offset] =3D > gb_tile_moden; > WREG32(mmGB_TILE_MODE0 + reg_offset, > gb_tile_moden); >=20 >=20 > -- > Jean Delvare > SUSE L3 Support