From: "Deucher, Alexander" <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>
To: "Liu, Monk" <Monk.Liu-5C7GfCeVMHo@public.gmane.org>,
Alex Deucher
<alexdeucher-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
"Yu, Xiangliang" <Xiangliang.Yu-5C7GfCeVMHo@public.gmane.org>
Cc: "dl.SRDC_SW_GPUVirtualization"
<dl.SRDC_SW_GPUVirtualization-5C7GfCeVMHo@public.gmane.org>,
"Min, Frank" <Frank.Min-5C7GfCeVMHo@public.gmane.org>,
amd-gfx list
<amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
Subject: RE: [PATCH 21/23] drm/amdgpu: change golden register program sequence of virtualization
Date: Tue, 20 Dec 2016 13:50:17 +0000 [thread overview]
Message-ID: <BN6PR12MB1652C93B278BF7B731612169F7900@BN6PR12MB1652.namprd12.prod.outlook.com> (raw)
In-Reply-To: <BY2PR12MB005449FC3CC2D91B41B3487884900-K//h7OWB4q7GdVlgMuSljQdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
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I don't mind keeping the list together.
Alex
From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf Of Liu, Monk
Sent: Monday, December 19, 2016 11:09 PM
To: Alex Deucher; Yu, Xiangliang
Cc: Min, Frank; dl.SRDC_SW_GPUVirtualization; amd-gfx list
Subject: 答复: [PATCH 21/23] drm/amdgpu: change golden register program sequence of virtualization
Hi Alex
I agree with you that this patch's GOLDEN setting programming should be put in VI.C, but I found a hardware issue :
original linux logic is that we set golden setting registers separately within each IP's hw init routine, but for TONGA VF, it is really strange that we must set all GOLDEN setting value to chip in one shoot (means we use one routine to programing all IP's golden setting to registers), ortherwise we found TONGA vf just failed in RING TEST.
and I admit I don't know why (I checked windows CAIL code, it is also set all golden setting registers in one routine)
BR Monk
________________________________
发件人: Alex Deucher <alexdeucher@gmail.com<mailto:alexdeucher@gmail.com>>
发送时间: 2016年12月20日 7:37:06
收件人: Yu, Xiangliang
抄送: amd-gfx list; dl.SRDC_SW_GPUVirtualization; Min, Frank; Liu, Monk
主题: Re: [PATCH 21/23] drm/amdgpu: change golden register program sequence of virtualization
On Sat, Dec 17, 2016 at 11:16 AM, Xiangliang Yu <Xiangliang.Yu@amd.com<mailto:Xiangliang.Yu@amd.com>> wrote:
> GPU virtualization has different sequence from normal, change it.
>
> Signed-off-by: Frank Min <Frank.Min@amd.com<mailto:Frank.Min@amd.com>>
> Signed-off-by: Monk Liu <Monk.Liu@amd.com<mailto:Monk.Liu@amd.com>>
> Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com<mailto:Xiangliang.Yu@amd.com>>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 2 +
> drivers/gpu/drm/amd/amdgpu/vi.c | 6 +
> drivers/gpu/drm/amd/mxgpu/mxgpu_vi.c | 267 +++++++++++++++++++++++++++++++
> 3 files changed, 275 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
> index eb2905e..e781c9c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
> @@ -84,4 +84,6 @@ int amdgpu_put_gpu(struct amdgpu_device *adev);
> /* access vf registers */
> uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);
> void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v);
> +
> +void amdgpu_xgpu_init_golden_registers(struct amdgpu_device *adev);
> #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
> index 5229b4a2a..0d5e807 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vi.c
> @@ -285,6 +285,12 @@ static void vi_init_golden_registers(struct amdgpu_device *adev)
> /* Some of the registers might be dependent on GRBM_GFX_INDEX */
> mutex_lock(&adev->grbm_idx_mutex);
>
> + if (adev->flags & AMD_IS_VF) {
> + amdgpu_xgpu_init_golden_registers(adev);
> + mutex_unlock(&adev->grbm_idx_mutex);
> + return;
> + }
> +
> switch (adev->asic_type) {
> case CHIP_TOPAZ:
> amdgpu_program_register_sequence(adev,
> diff --git a/drivers/gpu/drm/amd/mxgpu/mxgpu_vi.c b/drivers/gpu/drm/amd/mxgpu/mxgpu_vi.c
> index e5d517f..fa1ee8f 100644
> --- a/drivers/gpu/drm/amd/mxgpu/mxgpu_vi.c
> +++ b/drivers/gpu/drm/amd/mxgpu/mxgpu_vi.c
> @@ -42,6 +42,273 @@
> #include "dce/dce_10_0_sh_mask.h"
> #include "smu/smu_7_1_3_d.h"
>
> +static const u32 xgpu_fiji_mgcg_cgcg_init[] = {
> + mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
> + mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
> + mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
> + mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
> + mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
> + mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
> + mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
> + mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
> + mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
> + mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
> + mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
> + mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
> + mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
> + mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
> + mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
> + mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
> + mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
> + mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
> + mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
> + mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
> + mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
> + mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
> + mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
> + mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
> + mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
> + mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
> + mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
> + mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
> + mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
> + mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
> + mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
> + mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
> + mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
> + mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
> + mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
> + mmPCIE_INDEX, 0xffffffff, 0x0140001c,
> + mmPCIE_DATA, 0x000f0000, 0x00000000,
> + mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,
> + mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
> + mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
> + mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
> + mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104,
> + mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
> + mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
> + mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
> + mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
> + mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100,
> +};
> +
> +static const u32 xgpu_golden_settings_fiji_a10[] = {
> + mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
> + mmDB_DEBUG2, 0xf00fffff, 0x00000400,
> + mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
> + mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
> + mmFBC_MISC, 0x1f311fff, 0x12300000,
> + mmHDMI_CONTROL, 0x31000111, 0x00000011,
> + mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
> + mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
> + mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
> + mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
> + mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
> + mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
> + mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
> + mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
> + mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
> + mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
> + mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
> + mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
> + mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
> + mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000ff,
> + mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
> + mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
> + mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
> + mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
> + mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
> +};
> +
> +static const u32 xgpu_fiji_golden_common_all[] = {
> + mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
> + mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x3a00161a,
> + mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002e,
> + mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
> + mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
> + mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
> + mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
> + mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF,
> + mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
> + mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x00000009,
> +};
> +
> +static const u32 xgpu_tonga_mgcg_cgcg_init[] = {
> + mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
> + mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
> + mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
> + mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
> + mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
> + mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
> + mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
> + mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
> + mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
> + mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
> + mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
> + mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
> + mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
> + mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
> + mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
> + mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
> + mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
> + mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
> + mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
> + mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
> + mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
> + mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
> + mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
> + mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
> + mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
> + mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
> + mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
> + mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
> + mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
> + mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
> + mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
> + mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
> + mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
> + mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
> + mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
> + mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
> + mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
> + mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
> + mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
> + mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
> + mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
> + mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
> + mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
> + mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
> + mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
> + mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
> + mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
> + mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
> + mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
> + mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
> + mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
> + mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
> + mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
> + mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
> + mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
> + mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
> + mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
> + mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
> + mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
> + mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
> + mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
> + mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
> + mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
> + mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
> + mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
> + mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
> + mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
> + mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
> + mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
> + mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
> + mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
> + mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
> + mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
> + mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
> + mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
> + mmPCIE_INDEX, 0xffffffff, 0x0140001c,
> + mmPCIE_DATA, 0x000f0000, 0x00000000,
> + mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,
> + mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
> + mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
> + mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
> + mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104,
> + mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
> + mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
> + mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
> + mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
> + mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100,
> +};
> +
> +static const u32 xgpu_golden_settings_tonga_a11[] = {
> + mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208,
> + mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
> + mmDB_DEBUG2, 0xf00fffff, 0x00000400,
> + mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
> + mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
> + mmFBC_MISC, 0x1f311fff, 0x12300000,
> + mmGB_GPU_ID, 0x0000000f, 0x00000000,
> + mmHDMI_CONTROL, 0x31000111, 0x00000011,
> + mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
> + mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028,
> + mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991,
> + mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
> + mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc,
> + mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
> + mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
> + mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
> + mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
> + mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
> + mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
> + mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
> + mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
> + mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
> + mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
> + mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
> + mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
> + mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
> + mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
> + mmTCC_CTRL, 0x00100000, 0xf31fff7f,
> + mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
> + mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb,
> + mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b,
> + mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876,
> + mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
> + mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
> + mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
> + mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
> + mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
> +};
> +
> +static const u32 xgpu_tonga_golden_common_all[] = {
> + mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
> + mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
> + mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
> + mmGB_ADDR_CONFIG, 0xffffffff, 0x22011002,
> + mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
> + mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
> + mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
> +};
> +
> +void amdgpu_xgpu_init_golden_registers(struct amdgpu_device *adev)
> +{
> + switch (adev->asic_type) {
> + case CHIP_FIJI:
> + amdgpu_program_register_sequence(adev,
> + xgpu_fiji_mgcg_cgcg_init,
> + (const u32)ARRAY_SIZE(
> + xgpu_fiji_mgcg_cgcg_init));
> + amdgpu_program_register_sequence(adev,
> + xgpu_golden_settings_fiji_a10,
> + (const u32)ARRAY_SIZE(
> + xgpu_golden_settings_fiji_a10));
> + amdgpu_program_register_sequence(adev,
> + xgpu_fiji_golden_common_all,
> + (const u32)ARRAY_SIZE(
> + xgpu_fiji_golden_common_all));
> + break;
> + case CHIP_TONGA:
> + amdgpu_program_register_sequence(adev,
> + xgpu_tonga_mgcg_cgcg_init,
> + (const u32)ARRAY_SIZE(
> + xgpu_tonga_mgcg_cgcg_init));
> + amdgpu_program_register_sequence(adev,
> + xgpu_golden_settings_tonga_a11,
> + (const u32)ARRAY_SIZE(
> + xgpu_golden_settings_tonga_a11));
> + amdgpu_program_register_sequence(adev,
> + xgpu_tonga_golden_common_all,
> + (const u32)ARRAY_SIZE(
> + xgpu_tonga_golden_common_all));
> + break;
> + default:
> + break;
> + }
> +}
Cleaner to just put this in vi.c.
Alex
> +
> static int xgpu_vi_early_init(void *handle)
> {
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> --
> 2.7.4
>
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next prev parent reply other threads:[~2016-12-20 13:50 UTC|newest]
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2016-12-17 16:16 [PATCH 00/23] Add support AMD GPU virtualization soultion Xiangliang Yu
[not found] ` <1481991405-30422-1-git-send-email-Xiangliang.Yu-5C7GfCeVMHo@public.gmane.org>
2016-12-17 16:16 ` [PATCH 01/23] drm/amdgpu: add support kernel interface queue(KIQ) Xiangliang Yu
[not found] ` <1481991405-30422-2-git-send-email-Xiangliang.Yu-5C7GfCeVMHo@public.gmane.org>
2016-12-19 23:11 ` Alex Deucher
[not found] ` <CADnq5_P1An3GF9CJAdw5-av7oT0VDAN1YTgni9Q2waT81yyBtQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-12-20 5:32 ` Yu, Xiangliang
2016-12-17 16:16 ` [PATCH 02/23] drm/amdgpu: add kiq into compiling Xiangliang Yu
[not found] ` <CY4PR12MB170115ECFEEDEE2B92071FE7EB9E0@CY4PR12MB1701.namprd12.prod.outlook.com>
[not found] ` <CY4PR12MB170115ECFEEDEE2B92071FE7EB9E0-rpdhrqHFk05QaJCA3gGb3wdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2016-12-19 7:13 ` 转发: " Liu, Monk
[not found] ` <BY2PR12MB0054C15BB4903E12764EABF684910-K//h7OWB4q7GdVlgMuSljQdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2016-12-19 7:51 ` Yu, Xiangliang
2016-12-19 11:17 ` 转发: " Christian König
[not found] ` <beb83cf9-2683-569e-ea68-df3894e11dc0-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
2016-12-19 23:38 ` Alex Deucher
[not found] ` <CADnq5_MDTdnOcarCkDFdb5d=nJxDpt4ATkvmDG+BFG5thLa-eA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-12-20 3:43 ` 答复: " Liu, Monk
2016-12-20 5:26 ` Liu, Monk
2016-12-20 3:48 ` Mike Lothian
[not found] ` <CAHbf0-EqT1YHuxButQkfb8s3mGT4WjVdcjCWMFetiqwjEME8pA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-12-20 4:07 ` Bridgman, John
[not found] ` <BN6PR12MB13487A20F8218E81FB87B846E8900-/b2+HYfkarQX0pEhCR5T8QdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2016-12-23 10:47 ` Mike Lothian
2016-12-17 16:16 ` [PATCH 03/23] drm/amdgpu: export KIQ interfaces Xiangliang Yu
2016-12-17 16:16 ` [PATCH 04/23] drm/amdgpu: add new structure for KIQ memory allcation Xiangliang Yu
2016-12-17 16:16 ` [PATCH 05/23] drm/amdgpu/gfx8: add support KIQ for FIJI/TONGA chips Xiangliang Yu
2016-12-17 16:16 ` [PATCH 06/23] drm/amdgpu/gfx8: correct KIQ hdp flush Xiangliang Yu
[not found] ` <1481991405-30422-7-git-send-email-Xiangliang.Yu-5C7GfCeVMHo@public.gmane.org>
2016-12-19 23:13 ` Alex Deucher
2016-12-20 5:34 ` Yu, Xiangliang
2016-12-17 16:16 ` [PATCH 07/23] drm/amdgpu: create new directory for GPU virtualization Xiangliang Yu
[not found] ` <CY4PR12MB1701171F8B54171FCF66B30EEB9E0@CY4PR12MB1701.namprd12.prod.outlook.com>
[not found] ` <BY2PR12MB005475C762077C442361FBD284910@BY2PR12MB0054.namprd12.prod.outlook.com>
[not found] ` <CY4PR12MB1701DB3B08413BBDA717E73FEB910@CY4PR12MB1701.namprd12.prod.outlook.com>
[not found] ` <CY4PR12MB1701DB3B08413BBDA717E73FEB910-rpdhrqHFk05QaJCA3gGb3wdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2016-12-19 7:09 ` 转发: " Liu, Monk
2016-12-17 16:16 ` [PATCH 08/23] drm/amdgpu: add new flag for virtual function Xiangliang Yu
2016-12-17 16:16 ` [PATCH 09/23] drm/amdgpu: enable virtualization feature for FIJI/TONGA Xiangliang Yu
[not found] ` <1481991405-30422-10-git-send-email-Xiangliang.Yu-5C7GfCeVMHo@public.gmane.org>
2016-12-19 6:27 ` 答复: " Liu, Monk
2016-12-19 23:17 ` Alex Deucher
[not found] ` <CADnq5_PC6oukr7dzoi=wpWthUd9A-zx+-WDW8P0wm1zbRdnz1A-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-12-20 3:49 ` 答复: " Liu, Monk
2016-12-20 5:41 ` Yu, Xiangliang
[not found] ` <CY4PR12MB170197EFF75F8AB758618A21EB900-rpdhrqHFk05QaJCA3gGb3wdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2016-12-20 15:53 ` Deucher, Alexander
[not found] ` <BN6PR12MB1652A9F6AB1818BD6C7D3542F7900-/b2+HYfkarQqUD6E6FAiowdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2016-12-21 1:59 ` Yu, Xiangliang
[not found] ` <CY4PR12MB1701ACAA1FD55685C05F0B73EB930-rpdhrqHFk05QaJCA3gGb3wdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2016-12-22 9:48 ` Christian König
2016-12-17 16:16 ` [PATCH 10/23] drm/amdgpu: export gem va update interface Xiangliang Yu
2016-12-17 16:16 ` [PATCH 11/23] drm/amdgpu: implement context save area(CSA) feature Xiangliang Yu
[not found] ` <1481991405-30422-12-git-send-email-Xiangliang.Yu-5C7GfCeVMHo@public.gmane.org>
2016-12-19 23:20 ` Alex Deucher
[not found] ` <CADnq5_P1hOrd7Vk1G01Gj7aM1RjkyhgLGWV6CnTu9mvrGhtxsg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-12-20 3:57 ` 答复: " Liu, Monk
[not found] ` <BY2PR12MB00547F38C7E612AE3A4D027184900-K//h7OWB4q7GdVlgMuSljQdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2016-12-20 5:43 ` Yu, Xiangliang
[not found] ` <CY4PR12MB1701351D6DCEA18714735B3DEB900-rpdhrqHFk05QaJCA3gGb3wdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2017-01-03 14:30 ` Christian König
2016-12-17 16:16 ` [PATCH 12/23] drm/amdgpu: Insert meta data during submitting IB Xiangliang Yu
[not found] ` <1481991405-30422-13-git-send-email-Xiangliang.Yu-5C7GfCeVMHo@public.gmane.org>
2016-12-19 23:23 ` Alex Deucher
[not found] ` <CADnq5_M++bzSVb-58Mesk1eAyK7Phwfgnx-XGCtEGygAomP-iQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-12-20 5:53 ` Yu, Xiangliang
2016-12-17 16:16 ` [PATCH 13/23] drm/amdgpu/mxgpu: add support for mailbox communication Xiangliang Yu
[not found] ` <1481991405-30422-14-git-send-email-Xiangliang.Yu-5C7GfCeVMHo@public.gmane.org>
2016-12-19 23:24 ` Alex Deucher
[not found] ` <CADnq5_MZVK4c_eiYqoxxKSSPCtazki=0uB4bOAX8OjVKDnZCBg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-12-20 6:05 ` Yu, Xiangliang
[not found] ` <CY4PR12MB1701DEB3053096F2E9CD1416EB900-rpdhrqHFk05QaJCA3gGb3wdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2017-01-03 17:02 ` Liu, Shaoyun
2016-12-17 16:16 ` [PATCH 14/23] drm/amdgpu: export two mailbox interface to amdgpu Xiangliang Yu
2016-12-17 16:16 ` [PATCH 15/23] drm/amdgpu/mxgpu: implement register access function with KIQ Xiangliang Yu
[not found] ` <1481991405-30422-16-git-send-email-Xiangliang.Yu-5C7GfCeVMHo@public.gmane.org>
2016-12-19 23:26 ` Alex Deucher
[not found] ` <CADnq5_M2Mh-=wo0Aa-pS4P-59uLv6My0-LNn_Zuxy913MwhLbA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-12-20 6:08 ` Yu, Xiangliang
[not found] ` <CY4PR12MB170162420FF46FECF0D783B4EB900-rpdhrqHFk05QaJCA3gGb3wdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2016-12-20 13:59 ` Deucher, Alexander
2016-12-17 16:16 ` [PATCH 16/23] drm/amdgpu: add flag to indicate VF runtime state Xiangliang Yu
2016-12-17 16:16 ` [PATCH 17/23] drm/amdgpu: export vi common ip block Xiangliang Yu
[not found] ` <1481991405-30422-18-git-send-email-Xiangliang.Yu-5C7GfCeVMHo@public.gmane.org>
2016-12-19 23:27 ` Alex Deucher
2016-12-17 16:16 ` [PATCH 18/23] drm/amdgpu: add new maroc to identify virtualization " Xiangliang Yu
2016-12-17 16:16 ` [PATCH 19/23] drm/amdgpu/mxgpu: add implementation of GPU virtualization of VI Xiangliang Yu
[not found] ` <1481991405-30422-20-git-send-email-Xiangliang.Yu-5C7GfCeVMHo@public.gmane.org>
2016-12-19 23:34 ` Alex Deucher
[not found] ` <CADnq5_Oeoqx_MhuVODGz5ukU6qKWMU=v=VB9cV_jBd4V9HBKeg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-12-20 6:18 ` Yu, Xiangliang
2016-12-17 16:16 ` [PATCH 20/23] drm/amdgpu/mxgpu: enable VI virtualization Xiangliang Yu
[not found] ` <1481991405-30422-21-git-send-email-Xiangliang.Yu-5C7GfCeVMHo@public.gmane.org>
2016-12-19 23:08 ` Deucher, Alexander
[not found] ` <BN6PR12MB1652B3D6D0409C00F89F4493F7910-/b2+HYfkarQqUD6E6FAiowdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2016-12-20 5:29 ` Yu, Xiangliang
2016-12-17 16:16 ` [PATCH 21/23] drm/amdgpu: change golden register program sequence of virtualization Xiangliang Yu
[not found] ` <1481991405-30422-22-git-send-email-Xiangliang.Yu-5C7GfCeVMHo@public.gmane.org>
2016-12-19 23:37 ` Alex Deucher
[not found] ` <CADnq5_PqscSCAOGn+suNGkoUQdF5Z7O69wrL_CvH27hfKE4b0A-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-12-20 4:09 ` 答复: " Liu, Monk
[not found] ` <BY2PR12MB005449FC3CC2D91B41B3487884900-K//h7OWB4q7GdVlgMuSljQdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2016-12-20 6:09 ` Yu, Xiangliang
2016-12-20 13:50 ` Deucher, Alexander [this message]
2016-12-17 16:16 ` [PATCH 22/23] drm/amdgpu: do not reset gpu for virtualization Xiangliang Yu
2016-12-17 16:16 ` [PATCH 23/23] drm/amdgpu/mxgpu: add Makefie and Kconfig for GPU virtualization Xiangliang Yu
2016-12-19 5:15 ` 答复: [PATCH 00/23] Add support AMD GPU virtualization soultion Liu, Monk
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