RE: [PATCH] drm/amdgpu: fix vega10 graphic hang issue in S3 test

From: "Deucher, Alexander" <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>
To: "amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org"
	<amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
Cc: "Wang, Ken" <Ken.Wang-5C7GfCeVMHo@public.gmane.org>
Subject: RE: [PATCH] drm/amdgpu: fix vega10 graphic hang issue in S3 test
Date: Thu, 17 Aug 2017 12:41:56 +0000	[thread overview]
Message-ID: <BN6PR12MB1652EA435D77BD69832197A2F7830@BN6PR12MB1652.namprd12.prod.outlook.com> (raw)
In-Reply-To: <1502948583-25827-1-git-send-email-ken.wang-5C7GfCeVMHo@public.gmane.org>

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of ken.wang@amd.com
> Sent: Thursday, August 17, 2017 1:43 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Wang, Ken
> Subject: [PATCH] drm/amdgpu: fix vega10 graphic hang issue in S3 test
> 

Please include a better description.  E.g.,
mmVGT_INDEX_TYPE has no default value, need to make sure it's initialized when gfx is initialized.
With that fixed:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> From: Ken Wang <Ken.Wang@amd.com>
> 
> Change-Id: If01e32baa903c8c35991b1517c6d8bde98f5dae2
> Signed-off-by: Ken Wang <Ken.Wang@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 ++++++++--
>  drivers/gpu/drm/amd/amdgpu/soc15d.h   |  1 +
>  2 files changed, 9 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 1f6a34b..e183b50 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -1615,7 +1615,7 @@ static int gfx_v9_0_cp_gfx_start(struct
> amdgpu_device *adev)
>  	struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
>  	const struct cs_section_def *sect = NULL;
>  	const struct cs_extent_def *ext = NULL;
> -	int r, i;
> +	int r, i, tmp;
> 
>  	/* init the CP */
>  	WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev-
> >gfx.config.max_hw_contexts - 1);
> @@ -1623,7 +1623,7 @@ static int gfx_v9_0_cp_gfx_start(struct
> amdgpu_device *adev)
> 
>  	gfx_v9_0_cp_gfx_enable(adev, true);
> 
> -	r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4);
> +	r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3);
>  	if (r) {
>  		DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
>  		return r;
> @@ -1661,6 +1661,12 @@ static int gfx_v9_0_cp_gfx_start(struct
> amdgpu_device *adev)
>  	amdgpu_ring_write(ring, 0x8000);
>  	amdgpu_ring_write(ring, 0x8000);
> 
> +	amdgpu_ring_write(ring,
> PACKET3(PACKET3_SET_UCONFIG_REG,1));
> +	tmp = (PACKET3_SET_UCONFIG_REG_INDEX_TYPE |
> +		(SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) -
> PACKET3_SET_UCONFIG_REG_START));
> +	amdgpu_ring_write(ring, tmp);
> +	amdgpu_ring_write(ring, 0);
> +
>  	amdgpu_ring_commit(ring);
> 
>  	return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15d.h
> b/drivers/gpu/drm/amd/amdgpu/soc15d.h
> index ab94201..3b29827 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15d.h
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15d.h
> @@ -250,6 +250,7 @@
>  #define	PACKET3_SET_UCONFIG_REG				0x79
>  #define		PACKET3_SET_UCONFIG_REG_START
> 	0x0000c000
>  #define		PACKET3_SET_UCONFIG_REG_END
> 	0x0000c400
> +#define		PACKET3_SET_UCONFIG_REG_INDEX_TYPE
> 	(2 << 28)
>  #define	PACKET3_SCRATCH_RAM_WRITE			0x7D
>  #define	PACKET3_SCRATCH_RAM_READ			0x7E
>  #define	PACKET3_LOAD_CONST_RAM				0x80
> --
> 2.7.4
> 
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