The new PSP SOS firmware can support both A0 and A1.
Change-Id: I9bf85eb77b183a4403667c77e291e32689aed0af
---
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 12 +-----------
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index 61cf2f6954e7..f3f5d4dd4631 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -34,14 +34,11 @@
#include "nbio/nbio_7_4_offset.h"
MODULE_FIRMWARE("amdgpu/vega20_sos.bin");
-MODULE_FIRMWARE("amdgpu/vega20_sos_old.bin");
MODULE_FIRMWARE("amdgpu/vega20_ta.bin");
/* address block */
#define smnMP1_FIRMWARE_FLAGS 0x3010024
-#define VEGA20_BL_VERSION_VAR_NEW 0xA1
-
static int
psp_v11_0_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type)
{
@@ -104,7 +101,6 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
int err = 0;
const struct psp_firmware_header_v1_0 *sos_hdr;
const struct ta_firmware_header_v1_0 *ta_hdr;
- uint32_t bl_version;
DRM_DEBUG("\n");
@@ -116,13 +112,7 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
BUG();
}
- bl_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_100);
- bl_version = (bl_version & 0xFF0000) >> 16;
-
- if (bl_version == VEGA20_BL_VERSION_VAR_NEW)
- snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
- else
- snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos_old.bin", chip_name);
+ snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev);
if (err)
goto out;
--
2.19.2
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