From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Deucher, Alexander" Subject: Re: [PATCH] drm/amdgpu: disable UVD/VCE for some polaris 12 variants Date: Fri, 23 Nov 2018 19:32:49 +0000 Message-ID: References: <20181123083227.25555-1-Jerry.Zhang@amd.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0783204813==" Return-path: In-Reply-To: <20181123083227.25555-1-Jerry.Zhang-5C7GfCeVMHo@public.gmane.org> Content-Language: en-US List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "amd-gfx" To: "Zhang, Jerry" , "amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org" --===============0783204813== Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_BN6PR12MB18091B4409C1DC5CD17F903CF7D40BN6PR12MB1809namp_" --_000_BN6PR12MB18091B4409C1DC5CD17F903CF7D40BN6PR12MB1809namp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Is this required? Are the harvesting fuses incorrect? If the blocks are h= arvested, we should bail out of the blocks properly during init. Also, ple= ase make this more explicit if we still need it. E.g., if ((adev->pdev->device =3D=3D 0x67df) && (adev->pdev->revision =3D=3D 0xf7)) { /* Some polaris12 variants don't support UVD/VCE */ } else { amdgpu_device_ip_block_add(adev, &uvd_v6_3_ip_block); amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block); } That way if we re-arrange the order later, it will be easier to track. Alex ________________________________ From: amd-gfx on behalf of Junwei Z= hang Sent: Friday, November 23, 2018 3:32:27 AM To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Cc: Zhang, Jerry Subject: [PATCH] drm/amdgpu: disable UVD/VCE for some polaris 12 variants Some variants don't support UVD and VCE. Signed-off-by: Junwei Zhang --- drivers/gpu/drm/amd/amdgpu/vi.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/v= i.c index f3a4cf1f013a..3338b013ded4 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -1660,6 +1660,10 @@ int vi_set_ip_blocks(struct amdgpu_device *adev) amdgpu_device_ip_block_add(adev, &dce_v11_2_ip_blo= ck); amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block); amdgpu_device_ip_block_add(adev, &sdma_v3_1_ip_block); + /* Some polaris12 variants don't support UVD/VCE */ + if ((adev->pdev->device =3D=3D 0x67df) && + (adev->pdev->revision =3D=3D 0xf7)) + break; amdgpu_device_ip_block_add(adev, &uvd_v6_3_ip_block); amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block); break; -- 2.17.1 _______________________________________________ amd-gfx mailing list amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx --_000_BN6PR12MB18091B4409C1DC5CD17F903CF7D40BN6PR12MB1809namp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Is this required?  Are the h= arvesting fuses incorrect?  If the blocks are harvested, we should bai= l out of the blocks properly during init.  Also, please make this more= explicit if we still need it.  E.g.,


       if ((adev->pdev->device =3D=3D 0= x67df) &&
            &nb= sp; (adev->pdev->revision =3D=3D 0xf7)) {

        /* Some polaris12 variants= don't support UVD/VCE */

      } else  {

          = ;       amdgpu_device_ip_block_add(adev, &= ;uvd_v6_3_ip_block);

          = ;       amdgpu_device_ip_block_add(adev, &= ;vce_v3_4_ip_block);

    }


That way if we re-arrange the ord= er later, it will be easier to track.


Alex

From: amd-gfx <amd-gfx-b= ounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Junwei Zhang <Jerry.Zhang@= amd.com>
Sent: Friday, November 23, 2018 3:32:27 AM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Zhang, Jerry
Subject: [PATCH] drm/amdgpu: disable UVD/VCE for some polaris 12 var= iants
 
Some variants don't support UVD and VCE.

Signed-off-by: Junwei Zhang <Jerry.Zhang-5C7GfCeVMHo@public.gmane.org>
---
 drivers/gpu/drm/amd/amdgpu/vi.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/v= i.c
index f3a4cf1f013a..3338b013ded4 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -1660,6 +1660,10 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)=
            &nb= sp;            amdgp= u_device_ip_block_add(adev, &dce_v11_2_ip_block);
            &nb= sp;    amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_blo= ck);
            &nb= sp;    amdgpu_device_ip_block_add(adev, &sdma_v3_1_ip_bl= ock);
+           &nbs= p;   /* Some polaris12 variants don't support UVD/VCE */
+           &nbs= p;   if ((adev->pdev->device =3D=3D 0x67df) &&
+           &nbs= p;         (adev->pdev->revis= ion =3D=3D 0xf7))
+           &nbs= p;           break;
            &nb= sp;    amdgpu_device_ip_block_add(adev, &uvd_v6_3_ip_blo= ck);
            &nb= sp;    amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_blo= ck);
            &nb= sp;    break;
--
2.17.1

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