From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Deucher, Alexander" Subject: Re: [PATCH v2] drm/amd/display: fix Polaris 12 bw bounding box Date: Thu, 22 Mar 2018 18:51:53 +0000 Message-ID: References: <20180320191259.14453-10-harry.wentland@amd.com>, <20180322183957.11419-1-harry.wentland@amd.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1795752483==" Return-path: In-Reply-To: <20180322183957.11419-1-harry.wentland-5C7GfCeVMHo@public.gmane.org> Content-Language: en-US List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "amd-gfx" To: "Wentland, Harry" , "amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org" Cc: "Laktyushkin, Dmytro" --===============1795752483== Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_BN6PR12MB1809CA5F7C24F5115B7A8A3AF7A90BN6PR12MB1809namp_" --_000_BN6PR12MB1809CA5F7C24F5115B7A8A3AF7A90BN6PR12MB1809namp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Acked-by: Alex Deucher ________________________________ From: amd-gfx on behalf of Harry We= ntland Sent: Thursday, March 22, 2018 2:39:57 PM To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Cc: Laktyushkin, Dmytro; Wentland, Harry Subject: [PATCH v2] drm/amd/display: fix Polaris 12 bw bounding box From: Dmytro Laktyushkin Signed-off-by: Dmytro Laktyushkin Signed-off-by: Harry Wentland Reviewed-by: Bhawanpreet Lakha Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c | 121 +++++++++++++++++++= +++- drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h | 1 + 2 files changed, 120 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c b/drivers/gpu= /drm/amd/display/dc/calcs/dce_calcs.c index 0cbab81ab304..821502b1acba 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c @@ -52,10 +52,11 @@ static enum bw_calcs_version bw_calcs_version_from_asic= _id(struct hw_asic_id asi return BW_CALCS_VERSION_CARRIZO; case FAMILY_VI: + if (ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) + return BW_CALCS_VERSION_POLARIS12; if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev)) return BW_CALCS_VERSION_POLARIS10; - if (ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) || - ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal= _rev)) + if (ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev)) return BW_CALCS_VERSION_POLARIS11; return BW_CALCS_VERSION_INVALID; @@ -2373,6 +2374,122 @@ void bw_calcs_init(struct bw_calcs_dceip *bw_dceip, dceip.scatter_gather_pte_request_rows_in_tiling_mode =3D 2= ; dceip.mcifwr_all_surfaces_burst_time =3D bw_int_to_fixed(0= ); break; + case BW_CALCS_VERSION_POLARIS12: + vbios.memory_type =3D bw_def_gddr5; + vbios.dram_channel_width_in_bits =3D 32; + vbios.number_of_dram_channels =3D asic_id.vram_width / vbio= s.dram_channel_width_in_bits; + vbios.number_of_dram_banks =3D 8; + vbios.high_yclk =3D bw_int_to_fixed(6000); + vbios.mid_yclk =3D bw_int_to_fixed(3200); + vbios.low_yclk =3D bw_int_to_fixed(1000); + vbios.low_sclk =3D bw_int_to_fixed(678); + vbios.mid1_sclk =3D bw_int_to_fixed(864); + vbios.mid2_sclk =3D bw_int_to_fixed(900); + vbios.mid3_sclk =3D bw_int_to_fixed(920); + vbios.mid4_sclk =3D bw_int_to_fixed(940); + vbios.mid5_sclk =3D bw_int_to_fixed(960); + vbios.mid6_sclk =3D bw_int_to_fixed(980); + vbios.high_sclk =3D bw_int_to_fixed(1049); + vbios.low_voltage_max_dispclk =3D bw_int_to_fixed(459); + vbios.mid_voltage_max_dispclk =3D bw_int_to_fixed(654); + vbios.high_voltage_max_dispclk =3D bw_int_to_fixed(1108); + vbios.low_voltage_max_phyclk =3D bw_int_to_fixed(540); + vbios.mid_voltage_max_phyclk =3D bw_int_to_fixed(810); + vbios.high_voltage_max_phyclk =3D bw_int_to_fixed(810); + vbios.data_return_bus_width =3D bw_int_to_fixed(32); + vbios.trc =3D bw_int_to_fixed(48); + if (vbios.number_of_dram_channels =3D=3D 2) // 64-bit + vbios.dmifmc_urgent_latency =3D bw_int_to_fixed(4); + else + vbios.dmifmc_urgent_latency =3D bw_int_to_fixed(3); + vbios.stutter_self_refresh_exit_latency =3D bw_int_to_fixed= (5); + vbios.stutter_self_refresh_entry_latency =3D bw_int_to_fixe= d(0); + vbios.nbp_state_change_latency =3D bw_int_to_fixed(250); + vbios.mcifwrmc_urgent_latency =3D bw_int_to_fixed(10); + vbios.scatter_gather_enable =3D false; + vbios.down_spread_percentage =3D bw_frc_to_fixed(5, 10); + vbios.cursor_width =3D 32; + vbios.average_compression_rate =3D 4; + vbios.number_of_request_slots_gmc_reserves_for_dmif_per_cha= nnel =3D 256; + vbios.blackout_duration =3D bw_int_to_fixed(0); /* us */ + vbios.maximum_blackout_recovery_time =3D bw_int_to_fixed(0)= ; + + dceip.max_average_percent_of_ideal_port_bw_display_can_use_= in_normal_system_operation =3D 100; + dceip.max_average_percent_of_ideal_drambw_display_can_use_i= n_normal_system_operation =3D 100; + dceip.percent_of_ideal_port_bw_received_after_urgent_latenc= y =3D 100; + dceip.large_cursor =3D false; + dceip.dmif_request_buffer_size =3D bw_int_to_fixed(768); + dceip.dmif_pipe_en_fbc_chunk_tracker =3D false; + dceip.cursor_max_outstanding_group_num =3D 1; + dceip.lines_interleaved_into_lb =3D 2; + dceip.chunk_width =3D 256; + dceip.number_of_graphics_pipes =3D 5; + dceip.number_of_underlay_pipes =3D 0; + dceip.low_power_tiling_mode =3D 0; + dceip.display_write_back_supported =3D true; + dceip.argb_compression_support =3D true; + dceip.underlay_vscaler_efficiency6_bit_per_component =3D + bw_frc_to_fixed(35556, 10000); + dceip.underlay_vscaler_efficiency8_bit_per_component =3D + bw_frc_to_fixed(34286, 10000); + dceip.underlay_vscaler_efficiency10_bit_per_component =3D + bw_frc_to_fixed(32, 10); + dceip.underlay_vscaler_efficiency12_bit_per_component =3D + bw_int_to_fixed(3); + dceip.graphics_vscaler_efficiency6_bit_per_component =3D + bw_frc_to_fixed(35, 10); + dceip.graphics_vscaler_efficiency8_bit_per_component =3D + bw_frc_to_fixed(34286, 10000); + dceip.graphics_vscaler_efficiency10_bit_per_component =3D + bw_frc_to_fixed(32, 10); + dceip.graphics_vscaler_efficiency12_bit_per_component =3D + bw_int_to_fixed(3); + dceip.alpha_vscaler_efficiency =3D bw_int_to_fixed(3); + dceip.max_dmif_buffer_allocated =3D 4; + dceip.graphics_dmif_size =3D 12288; + dceip.underlay_luma_dmif_size =3D 19456; + dceip.underlay_chroma_dmif_size =3D 23552; + dceip.pre_downscaler_enabled =3D true; + dceip.underlay_downscale_prefetch_enabled =3D true; + dceip.lb_write_pixels_per_dispclk =3D bw_int_to_fixed(1); + dceip.lb_size_per_component444 =3D bw_int_to_fixed(245952); + dceip.graphics_lb_nodownscaling_multi_line_prefetching =3D = true; + dceip.stutter_and_dram_clock_state_change_gated_before_curs= or =3D + bw_int_to_fixed(1); + dceip.underlay420_luma_lb_size_per_component =3D bw_int_to_= fixed( + 82176); + dceip.underlay420_chroma_lb_size_per_component =3D + bw_int_to_fixed(164352); + dceip.underlay422_lb_size_per_component =3D bw_int_to_fixed= ( + 82176); + dceip.cursor_chunk_width =3D bw_int_to_fixed(64); + dceip.cursor_dcp_buffer_lines =3D bw_int_to_fixed(4); + dceip.underlay_maximum_width_efficient_for_tiling =3D + bw_int_to_fixed(1920); + dceip.underlay_maximum_height_efficient_for_tiling =3D + bw_int_to_fixed(1080); + dceip.peak_pte_request_to_eviction_ratio_limiting_multiple_= displays_or_single_rotated_display =3D + bw_frc_to_fixed(3, 10); + dceip.peak_pte_request_to_eviction_ratio_limiting_single_di= splay_no_rotation =3D + bw_int_to_fixed(25); + dceip.minimum_outstanding_pte_request_limit =3D bw_int_to_f= ixed( + 2); + dceip.maximum_total_outstanding_pte_requests_allowed_by_saw= =3D + bw_int_to_fixed(128); + dceip.limit_excessive_outstanding_dmif_requests =3D true; + dceip.linear_mode_line_request_alternation_slice =3D + bw_int_to_fixed(64); + dceip.scatter_gather_lines_of_pte_prefetching_in_linear_mod= e =3D + 32; + dceip.display_write_back420_luma_mcifwr_buffer_size =3D 122= 88; + dceip.display_write_back420_chroma_mcifwr_buffer_size =3D 8= 192; + dceip.request_efficiency =3D bw_frc_to_fixed(8, 10); + dceip.dispclk_per_request =3D bw_int_to_fixed(2); + dceip.dispclk_ramping_factor =3D bw_frc_to_fixed(105, 100); + dceip.display_pipe_throughput_factor =3D bw_frc_to_fixed(10= 5, 100); + dceip.scatter_gather_pte_request_rows_in_tiling_mode =3D 2; + dceip.mcifwr_all_surfaces_burst_time =3D bw_int_to_fixed(0)= ; + break; case BW_CALCS_VERSION_STONEY: vbios.memory_type =3D bw_def_gddr5; vbios.dram_channel_width_in_bits =3D 64; diff --git a/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h b/drivers/gpu/d= rm/amd/display/dc/inc/dce_calcs.h index a9bfe9ff8ce6..0bd87f24fc06 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h +++ b/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h @@ -42,6 +42,7 @@ enum bw_calcs_version { BW_CALCS_VERSION_CARRIZO, BW_CALCS_VERSION_POLARIS10, BW_CALCS_VERSION_POLARIS11, + BW_CALCS_VERSION_POLARIS12, BW_CALCS_VERSION_STONEY, BW_CALCS_VERSION_VEGA10 }; -- 2.14.1 _______________________________________________ amd-gfx mailing list amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx --_000_BN6PR12MB1809CA5F7C24F5115B7A8A3AF7A90BN6PR12MB1809namp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Acked-by: Alex Deucher <alexan= der.deucher-5C7GfCeVMHo@public.gmane.org>

From: amd-gfx <amd-gfx-b= ounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Harry Wentland <harry.went= land-5C7GfCeVMHo@public.gmane.org>
Sent: Thursday, March 22, 2018 2:39:57 PM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Laktyushkin, Dmytro; Wentland, Harry
Subject: [PATCH v2] drm/amd/display: fix Polaris 12 bw bounding box<= /font>
 
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@am= d.com>

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin-5C7GfCeVMHo@public.gmane.org>
Signed-off-by: Harry Wentland <harry.wentland-5C7GfCeVMHo@public.gmane.org>
Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha-5C7GfCeVMHo@public.gmane.org>
Acked-by: Harry Wentland <harry.wentland-5C7GfCeVMHo@public.gmane.org>
---
 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c | 121 +++= ;+++++++++++++++= ;++++-
 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h   | &nb= sp; 1 +
 2 files changed, 120 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c b/drivers/gpu= /drm/amd/display/dc/calcs/dce_calcs.c
index 0cbab81ab304..821502b1acba 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
@@ -52,10 +52,11 @@ static enum bw_calcs_version bw_calcs_version_from_= asic_id(struct hw_asic_id asi
            &nb= sp;    return BW_CALCS_VERSION_CARRIZO;
 
         case FAMILY_VI:
+           &nbs= p;   if (ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev))
+           &nbs= p;           return BW_CA= LCS_VERSION_POLARIS12;
            &nb= sp;    if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev))=
            &nb= sp;            retur= n BW_CALCS_VERSION_POLARIS10;
-            &n= bsp;  if (ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
-            &n= bsp;            = ;      ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal= _rev))
+           &nbs= p;   if (ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev))
            &nb= sp;            retur= n BW_CALCS_VERSION_POLARIS11;
            &nb= sp;    return BW_CALCS_VERSION_INVALID;
 
@@ -2373,6 +2374,122 @@ void bw_calcs_init(struct bw_calcs_dceip *bw_dc= eip,
            &nb= sp;    dceip.scatter_gather_pte_request_rows_in_tiling_mode = =3D 2;
            &nb= sp;    dceip.mcifwr_all_surfaces_burst_time =3D bw_int_to_fi= xed(0);
            &nb= sp;    break;
+       case BW_CALCS_VERSION_POLARIS12:<= br> +           &nbs= p;   vbios.memory_type =3D bw_def_gddr5;
+           &nbs= p;   vbios.dram_channel_width_in_bits =3D 32;
+           &nbs= p;   vbios.number_of_dram_channels =3D asic_id.vram_width / vbios= .dram_channel_width_in_bits;
+           &nbs= p;   vbios.number_of_dram_banks =3D 8;
+           &nbs= p;   vbios.high_yclk =3D bw_int_to_fixed(6000);
+           &nbs= p;   vbios.mid_yclk =3D bw_int_to_fixed(3200);
+           &nbs= p;   vbios.low_yclk =3D bw_int_to_fixed(1000);
+           &nbs= p;   vbios.low_sclk =3D bw_int_to_fixed(678);
+           &nbs= p;   vbios.mid1_sclk =3D bw_int_to_fixed(864);
+           &nbs= p;   vbios.mid2_sclk =3D bw_int_to_fixed(900);
+           &nbs= p;   vbios.mid3_sclk =3D bw_int_to_fixed(920);
+           &nbs= p;   vbios.mid4_sclk =3D bw_int_to_fixed(940);
+           &nbs= p;   vbios.mid5_sclk =3D bw_int_to_fixed(960);
+           &nbs= p;   vbios.mid6_sclk =3D bw_int_to_fixed(980);
+           &nbs= p;   vbios.high_sclk =3D bw_int_to_fixed(1049);
+           &nbs= p;   vbios.low_voltage_max_dispclk =3D bw_int_to_fixed(459);
+           &nbs= p;   vbios.mid_voltage_max_dispclk =3D bw_int_to_fixed(654);
+           &nbs= p;   vbios.high_voltage_max_dispclk =3D bw_int_to_fixed(1108); +           &nbs= p;   vbios.low_voltage_max_phyclk =3D bw_int_to_fixed(540);
+           &nbs= p;   vbios.mid_voltage_max_phyclk =3D bw_int_to_fixed(810);
+           &nbs= p;   vbios.high_voltage_max_phyclk =3D bw_int_to_fixed(810);
+           &nbs= p;   vbios.data_return_bus_width =3D bw_int_to_fixed(32);
+           &nbs= p;   vbios.trc =3D bw_int_to_fixed(48);
+           &nbs= p;   if (vbios.number_of_dram_channels =3D=3D 2) // 64-bit
+           &nbs= p;           vbios.dmifmc= _urgent_latency =3D bw_int_to_fixed(4);
+           &nbs= p;   else
+           &nbs= p;           vbios.dmifmc= _urgent_latency =3D bw_int_to_fixed(3);
+           &nbs= p;   vbios.stutter_self_refresh_exit_latency =3D bw_int_to_fixed(= 5);
+           &nbs= p;   vbios.stutter_self_refresh_entry_latency =3D bw_int_to_fixed= (0);
+           &nbs= p;   vbios.nbp_state_change_latency =3D bw_int_to_fixed(250);
+           &nbs= p;   vbios.mcifwrmc_urgent_latency =3D bw_int_to_fixed(10);
+           &nbs= p;   vbios.scatter_gather_enable =3D false;
+           &nbs= p;   vbios.down_spread_percentage =3D bw_frc_to_fixed(5, 10);
+           &nbs= p;   vbios.cursor_width =3D 32;
+           &nbs= p;   vbios.average_compression_rate =3D 4;
+           &nbs= p;   vbios.number_of_request_slots_gmc_reserves_for_dmif_per_chan= nel =3D 256;
+           &nbs= p;   vbios.blackout_duration =3D bw_int_to_fixed(0); /* us */
+           &nbs= p;   vbios.maximum_blackout_recovery_time =3D bw_int_to_fixed(0);=
+
+           &nbs= p;   dceip.max_average_percent_of_ideal_port_bw_display_can_use_i= n_normal_system_operation =3D 100;
+           &nbs= p;   dceip.max_average_percent_of_ideal_drambw_display_can_use_in= _normal_system_operation =3D 100;
+           &nbs= p;   dceip.percent_of_ideal_port_bw_received_after_urgent_latency= =3D 100;
+           &nbs= p;   dceip.large_cursor =3D false;
+           &nbs= p;   dceip.dmif_request_buffer_size =3D bw_int_to_fixed(768);
+           &nbs= p;   dceip.dmif_pipe_en_fbc_chunk_tracker =3D false;
+           &nbs= p;   dceip.cursor_max_outstanding_group_num =3D 1;
+           &nbs= p;   dceip.lines_interleaved_into_lb =3D 2;
+           &nbs= p;   dceip.chunk_width =3D 256;
+           &nbs= p;   dceip.number_of_graphics_pipes =3D 5;
+           &nbs= p;   dceip.number_of_underlay_pipes =3D 0;
+           &nbs= p;   dceip.low_power_tiling_mode =3D 0;
+           &nbs= p;   dceip.display_write_back_supported =3D true;
+           &nbs= p;   dceip.argb_compression_support =3D true;
+           &nbs= p;   dceip.underlay_vscaler_efficiency6_bit_per_component =3D
+           &nbs= p;           bw_frc_to_fi= xed(35556, 10000);
+           &nbs= p;   dceip.underlay_vscaler_efficiency8_bit_per_component =3D
+           &nbs= p;           bw_frc_to_fi= xed(34286, 10000);
+           &nbs= p;   dceip.underlay_vscaler_efficiency10_bit_per_component =3D +           &nbs= p;           bw_frc_to_fi= xed(32, 10);
+           &nbs= p;   dceip.underlay_vscaler_efficiency12_bit_per_component =3D +           &nbs= p;           bw_int_to_fi= xed(3);
+           &nbs= p;   dceip.graphics_vscaler_efficiency6_bit_per_component =3D
+           &nbs= p;           bw_frc_to_fi= xed(35, 10);
+           &nbs= p;   dceip.graphics_vscaler_efficiency8_bit_per_component =3D
+           &nbs= p;           bw_frc_to_fi= xed(34286, 10000);
+           &nbs= p;   dceip.graphics_vscaler_efficiency10_bit_per_component =3D +           &nbs= p;           bw_frc_to_fi= xed(32, 10);
+           &nbs= p;   dceip.graphics_vscaler_efficiency12_bit_per_component =3D +           &nbs= p;           bw_int_to_fi= xed(3);
+           &nbs= p;   dceip.alpha_vscaler_efficiency =3D bw_int_to_fixed(3);
+           &nbs= p;   dceip.max_dmif_buffer_allocated =3D 4;
+           &nbs= p;   dceip.graphics_dmif_size =3D 12288;
+           &nbs= p;   dceip.underlay_luma_dmif_size =3D 19456;
+           &nbs= p;   dceip.underlay_chroma_dmif_size =3D 23552;
+           &nbs= p;   dceip.pre_downscaler_enabled =3D true;
+           &nbs= p;   dceip.underlay_downscale_prefetch_enabled =3D true;
+           &nbs= p;   dceip.lb_write_pixels_per_dispclk =3D bw_int_to_fixed(1); +           &nbs= p;   dceip.lb_size_per_component444 =3D bw_int_to_fixed(245952);<= br> +           &nbs= p;   dceip.graphics_lb_nodownscaling_multi_line_prefetching =3D t= rue;
+           &nbs= p;   dceip.stutter_and_dram_clock_state_change_gated_before_curso= r =3D
+           &nbs= p;           bw_int_to_fi= xed(1);
+           &nbs= p;   dceip.underlay420_luma_lb_size_per_component =3D bw_int_to_f= ixed(
+           &nbs= p;           82176);
+           &nbs= p;   dceip.underlay420_chroma_lb_size_per_component =3D
+           &nbs= p;           bw_int_to_fi= xed(164352);
+           &nbs= p;   dceip.underlay422_lb_size_per_component =3D bw_int_to_fixed(=
+           &nbs= p;           82176);
+           &nbs= p;   dceip.cursor_chunk_width =3D bw_int_to_fixed(64);
+           &nbs= p;   dceip.cursor_dcp_buffer_lines =3D bw_int_to_fixed(4);
+           &nbs= p;   dceip.underlay_maximum_width_efficient_for_tiling =3D
+           &nbs= p;           bw_int_to_fi= xed(1920);
+           &nbs= p;   dceip.underlay_maximum_height_efficient_for_tiling =3D
+           &nbs= p;           bw_int_to_fi= xed(1080);
+           &nbs= p;   dceip.peak_pte_request_to_eviction_ratio_limiting_multiple_d= isplays_or_single_rotated_display =3D
+           &nbs= p;           bw_frc_to_fi= xed(3, 10);
+           &nbs= p;   dceip.peak_pte_request_to_eviction_ratio_limiting_single_dis= play_no_rotation =3D
+           &nbs= p;           bw_int_to_fi= xed(25);
+           &nbs= p;   dceip.minimum_outstanding_pte_request_limit =3D bw_int_to_fi= xed(
+           &nbs= p;           2);
+           &nbs= p;   dceip.maximum_total_outstanding_pte_requests_allowed_by_saw = =3D
+           &nbs= p;           bw_int_to_fi= xed(128);
+           &nbs= p;   dceip.limit_excessive_outstanding_dmif_requests =3D true; +           &nbs= p;   dceip.linear_mode_line_request_alternation_slice =3D
+           &nbs= p;           bw_int_to_fi= xed(64);
+           &nbs= p;   dceip.scatter_gather_lines_of_pte_prefetching_in_linear_mode= =3D
+           &nbs= p;           32;
+           &nbs= p;   dceip.display_write_back420_luma_mcifwr_buffer_size =3D 1228= 8;
+           &nbs= p;   dceip.display_write_back420_chroma_mcifwr_buffer_size =3D 81= 92;
+           &nbs= p;   dceip.request_efficiency =3D bw_frc_to_fixed(8, 10);
+           &nbs= p;   dceip.dispclk_per_request =3D bw_int_to_fixed(2);
+           &nbs= p;   dceip.dispclk_ramping_factor =3D bw_frc_to_fixed(105, 100);<= br> +           &nbs= p;   dceip.display_pipe_throughput_factor =3D bw_frc_to_fixed(105= , 100);
+           &nbs= p;   dceip.scatter_gather_pte_request_rows_in_tiling_mode =3D 2;<= br> +           &nbs= p;   dceip.mcifwr_all_surfaces_burst_time =3D bw_int_to_fixed(0);=
+           &nbs= p;   break;
         case BW_CALCS_VERSION_STON= EY:
            &nb= sp;    vbios.memory_type =3D bw_def_gddr5;
            &nb= sp;    vbios.dram_channel_width_in_bits =3D 64;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h b/drivers/gpu/d= rm/amd/display/dc/inc/dce_calcs.h
index a9bfe9ff8ce6..0bd87f24fc06 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h
@@ -42,6 +42,7 @@ enum bw_calcs_version {
         BW_CALCS_VERSION_CARRIZO,<= br>          BW_CALCS_VERSION_POLARIS10= ,
         BW_CALCS_VERSION_POLARIS11= ,
+       BW_CALCS_VERSION_POLARIS12,
         BW_CALCS_VERSION_STONEY,          BW_CALCS_VERSION_VEGA10  };
--
2.14.1

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