From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Deucher, Alexander" Subject: Re: [PATCH] drm/amdgpu: both support PCO FP5/AM4 rlc fw Date: Thu, 6 Dec 2018 02:45:45 +0000 Message-ID: References: <1544059612-3380-1-git-send-email-aaron.liu@amd.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1643584903==" Return-path: In-Reply-To: <1544059612-3380-1-git-send-email-aaron.liu-5C7GfCeVMHo@public.gmane.org> Content-Language: en-US List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "amd-gfx" To: "Liu, Aaron" , "amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org" --===============1643584903== Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_BN6PR12MB1809F17C96E262711D536C8BF7A90BN6PR12MB1809namp_" --_000_BN6PR12MB1809F17C96E262711D536C8BF7A90BN6PR12MB1809namp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Alex Deucher ________________________________ From: amd-gfx on behalf of Aaron Li= u Sent: Wednesday, December 5, 2018 8:26:52 PM To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Cc: Liu, Aaron Subject: [PATCH] drm/amdgpu: both support PCO FP5/AM4 rlc fw For Picasso && AM4 SOCKET board, we use picasso_rlc_am4.bin For Picasso && FP5 SOCKET board, we use picasso_rlc.bin Judgment method: PCO AM4: revision >=3D 0xC8 && revision <=3D 0xCF or revision >=3D 0xD8 && revision <=3D 0xDF otherwise is PCO FP5 Change-Id: I359f0a3d1bc7d4d49c871cb3fb82797c7b91b259 Signed-off-by: Aaron Liu --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/am= dgpu/gfx_v9_0.c index 94740ea..7556716 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -86,6 +86,7 @@ MODULE_FIRMWARE("amdgpu/picasso_me.bin"); MODULE_FIRMWARE("amdgpu/picasso_mec.bin"); MODULE_FIRMWARE("amdgpu/picasso_mec2.bin"); MODULE_FIRMWARE("amdgpu/picasso_rlc.bin"); +MODULE_FIRMWARE("amdgpu/picasso_rlc_am4.bin"); MODULE_FIRMWARE("amdgpu/raven2_ce.bin"); MODULE_FIRMWARE("amdgpu/raven2_pfp.bin"); @@ -645,7 +646,20 @@ static int gfx_v9_0_init_microcode(struct amdgpu_devic= e *adev) adev->gfx.ce_fw_version =3D le32_to_cpu(cp_hdr->header.ucode_versi= on); adev->gfx.ce_feature_version =3D le32_to_cpu(cp_hdr->ucode_feature= _version); - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); + /* + * For Picasso && AM4 SOCKET board, we use picasso_rlc_am4.bin + * instead of picasso_rlc.bin. + * Judgment method: + * PCO AM4: revision >=3D 0xC8 && revision <=3D 0xCF + * or revision >=3D 0xD8 && revision <=3D 0xDF + * otherwise is PCO FP5 + */ + if (!strcmp(chip_name, "picasso") && + (((adev->pdev->revision >=3D 0xC8) && (adev->pdev->revision= <=3D 0xCF)) || + ((adev->pdev->revision >=3D 0xD8) && (adev->pdev->revision = <=3D 0xDF)))) + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc_am4.bin",= chip_name); + else + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chi= p_name); err =3D request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); if (err) goto out; -- 2.7.4 _______________________________________________ amd-gfx mailing list amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx --_000_BN6PR12MB1809F17C96E262711D536C8BF7A90BN6PR12MB1809namp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Reviewed-by: Alex Deucher <ale= xander.deucher-5C7GfCeVMHo@public.gmane.org>

From: amd-gfx <amd-gfx-b= ounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Aaron Liu <aaron.liu@amd.c= om>
Sent: Wednesday, December 5, 2018 8:26:52 PM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Liu, Aaron
Subject: [PATCH] drm/amdgpu: both support PCO FP5/AM4 rlc fw
 
For Picasso && AM4 SOCKET board, we use pi= casso_rlc_am4.bin
For Picasso && FP5 SOCKET board, we use picasso_rlc.bin

Judgment method:
PCO AM4: revision >=3D 0xC8 && revision <=3D 0xCF
         or revision >=3D 0xD8 &= amp;& revision <=3D 0xDF
otherwise is PCO FP5

Change-Id: I359f0a3d1bc7d4d49c871cb3fb82797c7b91b259
Signed-off-by: Aaron Liu <aaron.liu-5C7GfCeVMHo@public.gmane.org>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 16 +++++&= #43;+++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/am= dgpu/gfx_v9_0.c
index 94740ea..7556716 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -86,6 +86,7 @@ MODULE_FIRMWARE("amdgpu/picasso_me.bin");  MODULE_FIRMWARE("amdgpu/picasso_mec.bin");
 MODULE_FIRMWARE("amdgpu/picasso_mec2.bin");
 MODULE_FIRMWARE("amdgpu/picasso_rlc.bin");
+MODULE_FIRMWARE("amdgpu/picasso_rlc_am4.bin");
 
 MODULE_FIRMWARE("amdgpu/raven2_ce.bin");
 MODULE_FIRMWARE("amdgpu/raven2_pfp.bin");
@@ -645,7 +646,20 @@ static int gfx_v9_0_init_microcode(struct amdgpu_d= evice *adev)
         adev->gfx.ce_fw_version= =3D le32_to_cpu(cp_hdr->header.ucode_version);
         adev->gfx.ce_feature_ve= rsion =3D le32_to_cpu(cp_hdr->ucode_feature_version);
 
-       snprintf(fw_name, sizeof(fw_name), &q= uot;amdgpu/%s_rlc.bin", chip_name);
+       /*
+        * For Picasso && AM= 4 SOCKET board, we use picasso_rlc_am4.bin
+        * instead of picasso_rlc.bi= n.
+        * Judgment method:
+        * PCO AM4: revision >=3D= 0xC8 && revision <=3D 0xCF
+        *    &n= bsp;     or revision >=3D 0xD8 && revision &= lt;=3D 0xDF
+        * otherwise is PCO FP5
+        */
+       if (!strcmp(chip_name, "pica= sso") &&
+           &nbs= p;   (((adev->pdev->revision >=3D 0xC8) && (adev= ->pdev->revision <=3D 0xCF)) ||
+           &nbs= p;   ((adev->pdev->revision >=3D 0xD8) && (adev-= >pdev->revision <=3D 0xDF))))
+           &nbs= p;   snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc_am4.b= in", chip_name);
+       else
+           &nbs= p;   snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin&q= uot;, chip_name);
         err =3D request_firmware(&= amp;adev->gfx.rlc_fw, fw_name, adev->dev);
         if (err)
            &nb= sp;    goto out;
--
2.7.4

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