From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57849) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH65W-000561-CW for qemu-devel@nongnu.org; Mon, 29 Oct 2018 07:52:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gH65T-0004KF-6x for qemu-devel@nongnu.org; Mon, 29 Oct 2018 07:52:06 -0400 Received: from mail-cys01nam02on0118.outbound.protection.outlook.com ([104.47.37.118]:14217 helo=NAM02-CY1-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gH65S-0004GJ-Tk for qemu-devel@nongnu.org; Mon, 29 Oct 2018 07:52:03 -0400 From: Aleksandar Markovic Date: Mon, 29 Oct 2018 11:52:00 +0000 Message-ID: References: <20181014142928.2784-1-f4bug@amsat.org> <20181014164140.GB2319@sx9> <20181015170202.GB2364@sx9> <20181016181916.GB2323@sx9>, <300f223b-2013-5e31-0dd1-cd9adf0948ba@linaro.org>, In-Reply-To: Content-Language: en-US Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [Qemu-devel] [PATCH] target/mips: Support Toshiba specific three-operand MADD and MADDU List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson , Fredrik Noring Cc: "Maciej W. Rozycki" , =?iso-8859-1?Q?Philippe_Mathieu-Daud=E9?= , Aurelien Jarno , "qemu-devel@nongnu.org Developers" , =?iso-8859-1?Q?J=FCrgen_Urban?= >=20 > From: Aleksandar Markovic > Subject: Re: [PATCH] target/mips: Support Toshiba specific three-operand = MADD and MADDU >=20 > > From: Richard Henderson > > Sent: Tuesday, October 16, 2018 8:37 PM > > Subject: Re: [PATCH] target/mips: Support Toshiba specific three-operan= d MADD and > MADDU > > > > On 10/16/18 11:19 AM, Fredrik Noring wrote: > > > /* global register indices */ > > > static TCGv cpu_gpr[32], cpu_PC; > > > static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC]; > > > > > > One option is to create a new array such as > > > > > > static TCGv_i64 mmi_gpr[32]; > > > > > > that represents the upper 64 bits of each GPR. Then cpu_gpr must be o= f > > > a 64-bit type too, even when QEMU runs in 32-bit user mode. The R5900 > > > does not implement CP0.Status.UX in hardware, though, so system mode = is > > > 64 bits, regardless. > > > > I would not implement r5900 for mips32 in that case, > > I would implement it only for TARGET_MIPS64. > > > > r~ >=20 > Hello, Richard. >=20 > I truly need your help here. As you can conclude from the discussion, R59= 00 folks > (anybody correct me if I am wrong) have some problems using any ABI other= than O32. > (For example, the standard gcc switch are "-mabi=3D32 -march=3Dr5900".) O= ther similar CPUs, > for example R4000, are built with TARGET_MIPS64, both user and system mod= e. R5900 > would not have TARGET_MIPS64 in such arrangement. This looks outlandish t= o me. Given > that R5900 is a 64-bit MIPS III-like processor, is there any anomaly in t= his > arrangement, or this should work and is OK? >=20 > Thanks, > Aleksandar >=20 Guys, Without TARGET_MIPS64, we can't say we emulate R5900 - we are emulating som= e other CPU that never existed. Convince me that I am wrong. Aleksandar=