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From: Aleksandar Markovic <amarkovic@wavecomp.com>
Date: Thu, 14 Feb 2019 18:58:57 +0000
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Subject: Re: [Qemu-devel] [PULL v2 07/12] target/mips: Update ITU to utilize
 SAARI and SAAR CP0 registers
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To: Peter Maydell <peter.maydell@linaro.org>, Aleksandar Markovic <aleksandar.markovic@rt-rk.com>
Cc: QEMU Developers <qemu-devel@nongnu.org>

> From: Peter Maydell <peter.maydell@linaro.org>
> Sent: Thursday, February 14, 2019 7:40 PM
> To: Aleksandar Markovic
> Cc: QEMU Developers; Aleksandar Markovic
> Subject: Re: [PULL v2 07/12] target/mips: Update ITU to utilize SAARI and=
 SAAR CP0 registers
>=20
> On Fri, 18 Jan 2019 at 16:59, Aleksandar Markovic
> <aleksandar.markovic@rt-rk.com> wrote:
> >
> > From: Yongbok Kim <yongbok.kim@mips.com>
> >
> > Update ITU to utilize SAARI and SAAR CP0 registers.
>=20
> Hi; Coverity complains (CID 1398648) about this bit of code:
>=20
> > -static void itc_reconfigure(MIPSITUState *tag)
> > +void itc_reconfigure(MIPSITUState *tag)
> >  {
> >      uint64_t *am =3D &tag->ITCAddressMap[0];
> >      MemoryRegion *mr =3D &tag->storage_io;
> > @@ -92,6 +92,12 @@ static void itc_reconfigure(MIPSITUState *tag)
> >      uint64_t size =3D (1 * KiB) + (am[1] & ITC_AM1_ADDR_MASK_MASK);
> >      bool is_enabled =3D (am[0] & ITC_AM0_EN_MASK) !=3D 0;
> >
> > +    if (tag->saar_present) {
> > +        address =3D ((*(uint64_t *) tag->saar) & 0xFFFFFFFFE000ULL) <<=
 4;
> > +        size =3D 1 << ((*(uint64_t *) tag->saar >> 1) & 0x1f);
> > +        is_enabled =3D *(uint64_t *) tag->saar & 1;
> > +    }
> > +
>=20
> because the "1 << ..." calculation of size is done as a 32-bit
> signed integer which may then be unintentionally sign-extended
> into the 64-bit result. Using "1ULL" instead of "1" on the LHS
> of the shift would fix this.
>=20

Thanks, I'll try to integrate the fix soon.

Aleksandar

> thanks
> -- PMM
 =