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From: Aleksandar Markovic <amarkovic@wavecomp.com>
Date: Wed, 5 Sep 2018 17:21:21 +0000
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Subject: Re: [Qemu-devel] [PATCH v4 3/9] target/mips: Split mips instruction
 handling
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To: "Janeczek, Craig" <jancraig@amazon.com>, "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Cc: "aurelien@aurel32.net" <aurelien@aurel32.net>, Petar Jovanovic <pjovanovic@wavecomp.com>, Richard Henderson <richard.henderson@linaro.org>

> From: Janeczek, Craig <jancraig@amazon.com>
> Sent: Tuesday, September 4, 2018 4:44 PM
>
> Subject: RE: [PATCH v4 3/9] target/mips: Split mips instruction handling
>
> To clarify the OPC_MUL here is not an MXU instruction, this is the origin=
al OPC_MUL that was in the special2 instruction set. The inclusion of this =
instruction in this switch statement is due to the suggested method of spli=
tting up the mxu commands instruction handling switch statement from the or=
iginal special2 commands.

There are five more cases where current SPECIAL2 instructions occupy free s=
lots in  MXU opcode scheme:

    /* Loongson 2F */
    OPC_MODU_G_2F   =3D 0x1e | OPC_SPECIAL2,
    OPC_DMODU_G_2F  =3D 0x1f | OPC_SPECIAL2,
    /* Misc */
    OPC_CLZ      =3D 0x20 | OPC_SPECIAL2,
    OPC_CLO      =3D 0x21 | OPC_SPECIAL2,
    /* Special */
    OPC_SDBBP =3D 0x3F | OPC_SPECIAL2,

What to do with them? Should they be treated like OPC_MUL? Can you do the s=
ame binary check as for OPC_MUL? Is there a confirmation in Ingenic gcc/asm=
 source for all these cases?

Thanks,
Aleksandar=