From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36671) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpHLC-0008M4-7v for qemu-devel@nongnu.org; Mon, 13 Aug 2018 14:13:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fpHL9-0007IJ-0W for qemu-devel@nongnu.org; Mon, 13 Aug 2018 14:13:18 -0400 Received: from mail-by2nam01on0110.outbound.protection.outlook.com ([104.47.34.110]:27566 helo=NAM01-BY2-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fpHL8-0007HV-DR for qemu-devel@nongnu.org; Mon, 13 Aug 2018 14:13:14 -0400 From: Aleksandar Markovic Date: Mon, 13 Aug 2018 18:13:06 +0000 Message-ID: References: <1534182832-554-1-git-send-email-aleksandar.markovic@rt-rk.com>, <1534182832-554-10-git-send-email-aleksandar.markovic@rt-rk.com> In-Reply-To: <1534182832-554-10-git-send-email-aleksandar.markovic@rt-rk.com> Content-Language: en-US Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [Qemu-devel] [PATCH v8 09/87] target/mips: Add support for availability control via bit MT List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Aleksandar Markovic , "qemu-devel@nongnu.org" Cc: "peter.maydell@linaro.org" , "laurent@vivier.eu" , "riku.voipio@iki.fi" , "philippe.mathieu.daude@gmail.com" , "aurelien@aurel32.net" , "richard.henderson@linaro.org" , Stefan Markovic , Petar Jovanovic , Paul Burton > From: Aleksandar Markovic > Sent: Monday, August 13, 2018 7:52 PM >=20 > Subject: [PATCH v8 09/87] target/mips: Add support for availability contr= ol via bit MT >=20 > From: Aleksandar Rikalo >=20 > Add a field in hflags for MT bit, and functions check_mt() and > check_cp0_mt(). >=20 > Signed-off-by: Aleksandar Markovic > Signed-off-by: Stefan Markovic > --- > target/mips/cpu.h | 3 ++- > target/mips/internal.h | 6 +++++- > target/mips/translate.c | 29 +++++++++++++++++++++++++++++ > 3 files changed, 36 insertions(+), 2 deletions(-) >=20 > diff --git a/target/mips/cpu.h b/target/mips/cpu.h > ... > +/* > + * This code generates a "coprocessor unusable" if CP) is not > + * available, and, if that is not the case, generates a "reserved > + * instruction" exception if the Config5 MT bit is NOT set. > + * This is used for some of instructions in MT ASE. > + */ " "coprocessor unusable" if CP) " should be " "coprocessor unusable" except= ion if CP0 ". Otherwise: Reviewed-by: Aleksandar Markovic