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charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" > From: Jean-Philippe Brucker > Sent: Tuesday, June 28, 2022 5:44 PM > > On Tue, Jun 28, 2022 at 08:39:36AM +0000, Tian, Kevin wrote: > > > From: Lu Baolu > > > Sent: Tuesday, June 21, 2022 10:44 PM > > > > > > Tweak the I/O page fault handling framework to route the page faults to > > > the domain and call the page fault handler retrieved from the domain. > > > This makes the I/O page fault handling framework possible to serve more > > > usage scenarios as long as they have an IOMMU domain and install a > page > > > fault handler in it. Some unused functions are also removed to avoid > > > dead code. > > > > > > The iommu_get_domain_for_dev_pasid() which retrieves attached > domain > > > for a {device, PASID} pair is used. It will be used by the page fault > > > handling framework which knows {device, PASID} reported from the > iommu > > > driver. We have a guarantee that the SVA domain doesn't go away during > > > IOPF handling, because unbind() waits for pending faults with > > > iopf_queue_flush_dev() before freeing the domain. Hence, there's no > need > > > to synchronize life cycle of the iommu domains between the unbind() and > > > the interrupt threads. > > > > I found iopf_queue_flush_dev() is only called in intel-iommu driver. Did > > I overlook anything? > > The SMMU driver will need it as well when we upstream PRI support. > Currently it only supports stall, and that requires the device driver to > flush all DMA including stalled transactions *before* calling unbind(), so > ne need for iopf_queue_flush_dev() in this case. > then it makes sense. Probably Baolu can add this information in the commit msg so others with similar question can quickly get the point here. _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B8842C43334 for ; Tue, 28 Jun 2022 10:03:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344541AbiF1KDF (ORCPT ); Tue, 28 Jun 2022 06:03:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57582 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344635AbiF1KCi (ORCPT ); Tue, 28 Jun 2022 06:02:38 -0400 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8D9702F392 for ; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BN9PR11MB5276.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7d53f580-1957-4a95-96f5-08da58ed3ecb X-MS-Exchange-CrossTenant-originalarrivaltime: 28 Jun 2022 10:02:01.0057 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: JhruxJsMyA+EDjTgD852OKGfmWnZkpFNEAfxFfYDvH48v6WQ1b+wVbjuAvbl+9WpRdCglVIq75UsPghvURTizA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR11MB4740 X-OriginatorOrg: intel.com Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > From: Jean-Philippe Brucker > Sent: Tuesday, June 28, 2022 5:44 PM >=20 > On Tue, Jun 28, 2022 at 08:39:36AM +0000, Tian, Kevin wrote: > > > From: Lu Baolu > > > Sent: Tuesday, June 21, 2022 10:44 PM > > > > > > Tweak the I/O page fault handling framework to route the page faults = to > > > the domain and call the page fault handler retrieved from the domain. > > > This makes the I/O page fault handling framework possible to serve mo= re > > > usage scenarios as long as they have an IOMMU domain and install a > page > > > fault handler in it. Some unused functions are also removed to avoid > > > dead code. > > > > > > The iommu_get_domain_for_dev_pasid() which retrieves attached > domain > > > for a {device, PASID} pair is used. It will be used by the page fault > > > handling framework which knows {device, PASID} reported from the > iommu > > > driver. We have a guarantee that the SVA domain doesn't go away durin= g > > > IOPF handling, because unbind() waits for pending faults with > > > iopf_queue_flush_dev() before freeing the domain. Hence, there's no > need > > > to synchronize life cycle of the iommu domains between the unbind() a= nd > > > the interrupt threads. > > > > I found iopf_queue_flush_dev() is only called in intel-iommu driver. Di= d > > I overlook anything? >=20 > The SMMU driver will need it as well when we upstream PRI support. > Currently it only supports stall, and that requires the device driver to > flush all DMA including stalled transactions *before* calling unbind(), s= o > ne need for iopf_queue_flush_dev() in this case. > then it makes sense. Probably Baolu can add this information in the commit msg so others with similar question can quickly get the point here.