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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BN9PR11MB5276.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: e67d9712-6dfa-407e-133b-08da0e269d65 X-MS-Exchange-CrossTenant-originalarrivaltime: 25 Mar 2022 06:13:43.7758 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: yeB7ZYd18aefY4X+UXmu5e++pA0rQ4qGPGbNiXWfvXtbRdqirflbwaMbVjrOYuI0EyQCV7ktuC58Z7z1d+ruTQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR11MB4895 X-OriginatorOrg: intel.com Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > From: David Stevens > Sent: Tuesday, March 22, 2022 2:36 PM >=20 > From: David Stevens >=20 > Calculate the appropriate mask for non-size-aligned page selective > invalidation. Since psi uses the mask value to mask out the lower order > bits of the target address, properly flushing the iotlb requires using a > mask value such that [pfn, pfn+pages) all lie within the flushed > size-aligned region. This is not normally an issue because iova.c > always allocates iovas that are aligned to their size. However, iovas > which come from other sources (e.g. userspace via VFIO) may not be > aligned. >=20 > Signed-off-by: David Stevens > --- > v1 -> v2: > - Calculate an appropriate mask for non-size-aligned iovas instead > of falling back to domain selective flush. >=20 > drivers/iommu/intel/iommu.c | 27 ++++++++++++++++++++++++--- > 1 file changed, 24 insertions(+), 3 deletions(-) >=20 > diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c > index 5b196cfe9ed2..ab2273300346 100644 > --- a/drivers/iommu/intel/iommu.c > +++ b/drivers/iommu/intel/iommu.c > @@ -1717,7 +1717,8 @@ static void iommu_flush_iotlb_psi(struct > intel_iommu *iommu, > unsigned long pfn, unsigned int pages, > int ih, int map) > { > - unsigned int mask =3D ilog2(__roundup_pow_of_two(pages)); > + unsigned int aligned_pages =3D __roundup_pow_of_two(pages); > + unsigned int mask =3D ilog2(aligned_pages); > uint64_t addr =3D (uint64_t)pfn << VTD_PAGE_SHIFT; > u16 did =3D domain->iommu_did[iommu->seq_id]; >=20 > @@ -1729,10 +1730,30 @@ static void iommu_flush_iotlb_psi(struct > intel_iommu *iommu, > if (domain_use_first_level(domain)) { > domain_flush_piotlb(iommu, domain, addr, pages, ih); > } else { > + unsigned long bitmask =3D aligned_pages - 1; > + > + /* > + * PSI masks the low order bits of the base address. If the > + * address isn't aligned to the mask, then compute a mask > value > + * needed to ensure the target range is flushed. > + */ > + if (unlikely(bitmask & pfn)) { > + unsigned long end_pfn =3D pfn + pages - 1, shared_bits; > + > + /* > + * Since end_pfn <=3D pfn + bitmask, the only way bits > + * higher than bitmask can differ in pfn and end_pfn > is > + * by carrying. This means after masking out bitmask, > + * high bits starting with the first set bit in > + * shared_bits are all equal in both pfn and end_pfn. > + */ > + shared_bits =3D ~(pfn ^ end_pfn) & ~bitmask; > + mask =3D shared_bits ? __ffs(shared_bits) : > BITS_PER_LONG; > + } While it works I wonder whether below is simpler regarding to readability: } else { + /* + * PSI masks the low order bits of the base address. If the + * address isn't aligned to the mask and [pfn, pfn+pages) + * don't all lie within the flushed size-aligned region, + * simply increment the mask by one to cover the trailing pages. + */ + if (unlikely((pfn & (aligned_pages - 1)) && + (pfn + pages - 1 >=3D ALIGN(pfn, aligned_pages)))) + mask++; Thanks Kevin From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp2.osuosl.org (smtp2.osuosl.org [140.211.166.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 16CF2C433EF for ; Fri, 25 Mar 2022 06:13:51 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by smtp2.osuosl.org (Postfix) with ESMTP id A4AB94040D; Fri, 25 Mar 2022 06:13:51 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from smtp2.osuosl.org ([127.0.0.1]) by localhost (smtp2.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id LjH5ktLujTIu; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" > From: David Stevens > Sent: Tuesday, March 22, 2022 2:36 PM > > From: David Stevens > > Calculate the appropriate mask for non-size-aligned page selective > invalidation. Since psi uses the mask value to mask out the lower order > bits of the target address, properly flushing the iotlb requires using a > mask value such that [pfn, pfn+pages) all lie within the flushed > size-aligned region. This is not normally an issue because iova.c > always allocates iovas that are aligned to their size. However, iovas > which come from other sources (e.g. userspace via VFIO) may not be > aligned. > > Signed-off-by: David Stevens > --- > v1 -> v2: > - Calculate an appropriate mask for non-size-aligned iovas instead > of falling back to domain selective flush. > > drivers/iommu/intel/iommu.c | 27 ++++++++++++++++++++++++--- > 1 file changed, 24 insertions(+), 3 deletions(-) > > diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c > index 5b196cfe9ed2..ab2273300346 100644 > --- a/drivers/iommu/intel/iommu.c > +++ b/drivers/iommu/intel/iommu.c > @@ -1717,7 +1717,8 @@ static void iommu_flush_iotlb_psi(struct > intel_iommu *iommu, > unsigned long pfn, unsigned int pages, > int ih, int map) > { > - unsigned int mask = ilog2(__roundup_pow_of_two(pages)); > + unsigned int aligned_pages = __roundup_pow_of_two(pages); > + unsigned int mask = ilog2(aligned_pages); > uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT; > u16 did = domain->iommu_did[iommu->seq_id]; > > @@ -1729,10 +1730,30 @@ static void iommu_flush_iotlb_psi(struct > intel_iommu *iommu, > if (domain_use_first_level(domain)) { > domain_flush_piotlb(iommu, domain, addr, pages, ih); > } else { > + unsigned long bitmask = aligned_pages - 1; > + > + /* > + * PSI masks the low order bits of the base address. If the > + * address isn't aligned to the mask, then compute a mask > value > + * needed to ensure the target range is flushed. > + */ > + if (unlikely(bitmask & pfn)) { > + unsigned long end_pfn = pfn + pages - 1, shared_bits; > + > + /* > + * Since end_pfn <= pfn + bitmask, the only way bits > + * higher than bitmask can differ in pfn and end_pfn > is > + * by carrying. This means after masking out bitmask, > + * high bits starting with the first set bit in > + * shared_bits are all equal in both pfn and end_pfn. > + */ > + shared_bits = ~(pfn ^ end_pfn) & ~bitmask; > + mask = shared_bits ? __ffs(shared_bits) : > BITS_PER_LONG; > + } While it works I wonder whether below is simpler regarding to readability: } else { + /* + * PSI masks the low order bits of the base address. If the + * address isn't aligned to the mask and [pfn, pfn+pages) + * don't all lie within the flushed size-aligned region, + * simply increment the mask by one to cover the trailing pages. + */ + if (unlikely((pfn & (aligned_pages - 1)) && + (pfn + pages - 1 >= ALIGN(pfn, aligned_pages)))) + mask++; Thanks Kevin _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu