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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BN9PR12MB5257.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: e2814880-4d09-4184-c4de-08d9db44958b X-MS-Exchange-CrossTenant-originalarrivaltime: 19 Jan 2022 12:09:46.1297 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: MfvXoHL9FUQFB2G0oaWVXEQjRgrRzuoc2N9Gg3Pjfg9LVf1Dcm4cWnoyA78yBu8vLfjkKN4IruulNoef+5uKdw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB2728 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Yang, Stanley" Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" [AMD Official Use Only] The change made in drivers/gpu/drm/amd/amdgpu/umc_v8_7.c looks already cove= red by Zafar's change. Other than that, the patch looks good to me. Reviewed-by: Hawking Zhang Regards, Hawking -----Original Message----- From: Stanley.Yang =20 Sent: Wednesday, January 19, 2022 19:31 To: amd-gfx@lists.freedesktop.org; Zhang, Hawking ; = Ziya, Mohammad zafar ; Clements, John ; Zhou1, Tao Cc: Yang, Stanley Subject: [PATCH Review 1/1] drm/amdgpu: remove unused variable warning Change-Id: Ic2a488ee253a913d806bd33ee9c90e31a71af320 Signed-off-by: Stanley.Yang --- drivers/gpu/drm/amd/amdgpu/umc_v6_7.c | 23 ----------------------- driver= s/gpu/drm/amd/amdgpu/umc_v8_7.c | 6 ------ 2 files changed, 29 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c b/drivers/gpu/drm/amd/am= dgpu/umc_v6_7.c index 6953426f0bed..526de1ca9b8d 100644 --- a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c +++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c @@ -61,22 +61,9 @@ static void umc_v6_7_ecc_info_query_correctable_error_co= unt(struct amdgpu_device uint32_t channel_index, unsigned long *error_count) { - uint32_t ecc_err_cnt; uint64_t mc_umc_status; struct amdgpu_ras *ras =3D amdgpu_ras_get_context(adev); =20 - /* - * select the lower chip and check the error count - * skip add error count, calc error counter only from mca_umc_status - */ - ecc_err_cnt =3D ras->umc_ecc.ecc[channel_index].ce_count_lo_chip; - - /* - * select the higher chip and check the err counter - * skip add error count, calc error counter only from mca_umc_status - */ - ecc_err_cnt =3D ras->umc_ecc.ecc[channel_index].ce_count_hi_chip; - /* check for SRAM correctable error MCUMC_STATUS is a 64 bit register */ mc_umc_status =3D ras->umc_ecc.ecc[channel_index].mca_umc_status; @@ -110,15 +97,11 @@ static void umc_v6_7_ecc_info_query_ras_error_count(st= ruct amdgpu_device *adev, =20 uint32_t umc_inst =3D 0; uint32_t ch_inst =3D 0; - uint32_t umc_reg_offset =3D 0; uint32_t channel_index =3D 0; =20 /*TODO: driver needs to toggle DF Cstate to ensure * safe access of UMC registers. Will add the protection */ LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) { - umc_reg_offset =3D get_umc_v6_7_reg_offset(adev, - umc_inst, - ch_inst); channel_index =3D get_umc_v6_7_channel_index(adev, umc_inst, ch_inst); @@ -133,7 +116,6 @@ static void umc_v6_7_ecc_info_query_ras_error_count(str= uct amdgpu_device *adev, =20 static void umc_v6_7_ecc_info_query_error_address(struct amdgpu_device *ad= ev, struct ras_err_data *err_data, - uint32_t umc_reg_offset, uint32_t ch_inst, uint32_t umc_inst) { @@ -192,18 +174,13 @@ static void umc_v6_7_ecc_info_query_ras_error_address= (struct amdgpu_device *adev =20 uint32_t umc_inst =3D 0; uint32_t ch_inst =3D 0; - uint32_t umc_reg_offset =3D 0; =20 /*TODO: driver needs to toggle DF Cstate to ensure * safe access of UMC resgisters. Will add the protection * when firmware interface is ready */ LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) { - umc_reg_offset =3D get_umc_v6_7_reg_offset(adev, - umc_inst, - ch_inst); umc_v6_7_ecc_info_query_error_address(adev, err_data, - umc_reg_offset, ch_inst, umc_inst); } diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v8_7.c b/drivers/gpu/drm/amd/am= dgpu/umc_v8_7.c index 05f79eea307c..cd57f39df7d1 100644 --- a/drivers/gpu/drm/amd/amdgpu/umc_v8_7.c +++ b/drivers/gpu/drm/amd/amdgpu/umc_v8_7.c @@ -114,7 +114,6 @@ static void umc_v8_7_ecc_info_query_ras_error_count(str= uct amdgpu_device *adev, =20 static void umc_v8_7_ecc_info_query_error_address(struct amdgpu_device *ad= ev, struct ras_err_data *err_data, - uint32_t umc_reg_offset, uint32_t ch_inst, uint32_t umc_inst) { @@ -173,19 +172,14 @@ static void umc_v8_7_ecc_info_query_ras_error_address= (struct amdgpu_device *adev =20 uint32_t umc_inst =3D 0; uint32_t ch_inst =3D 0; - uint32_t umc_reg_offset =3D 0; =20 /* TODO: driver needs to toggle DF Cstate to ensure * safe access of UMC resgisters. Will add the protection * when firmware interface is ready */ LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) { - umc_reg_offset =3D get_umc_v8_7_reg_offset(adev, - umc_inst, - ch_inst); umc_v8_7_ecc_info_query_error_address(adev, err_data, - umc_reg_offset, ch_inst, umc_inst); } -- 2.17.1