From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Liu, Monk" Subject: =?gb2312?B?tPC4tDogW1BBVENIIDMvM10gZHJtL2FtZGdwdTppbnZva2UgbWV0YS1kYXRh?= =?gb2312?Q?_write_around_cntx=5Fcntl?= Date: Mon, 16 Jan 2017 08:21:22 +0000 Message-ID: References: <1484206893-18806-1-git-send-email-Monk.Liu@amd.com> <1484206893-18806-4-git-send-email-Monk.Liu@amd.com> , Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1887758279==" Return-path: In-Reply-To: Content-Language: zh-CN List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "amd-gfx" To: Alex Deucher Cc: amd-gfx list --===============1887758279== Content-Language: zh-CN Content-Type: multipart/alternative; boundary="_000_BY2PR1201MB1110254EE3F6E5B71C41201C847D0BY2PR1201MB1110_" --_000_BY2PR1201MB1110254EE3F6E5B71C41201C847D0BY2PR1201MB1110_ Content-Type: text/plain; charset="gb2312" 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okay, thanks

=B7=A2=BC=FE=C8=CB: Alex = Deucher <alexdeucher-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
=B7=A2=CB=CD=CA=B1=BC=E4: 2017=C4=EA1=D4=C214=C8=D5 0:35:45
=CA=D5=BC=FE=C8=CB: Liu, Monk
=B3=AD=CB=CD: amd-gfx list
=D6=F7=CC=E2: Re: [PATCH 3/3] drm/amdgpu:invoke meta-data write arou= nd cntx_cntl
 
On Fri, Jan 13, 2017 at 11:28 AM, Alex Deucher <= ;alexdeucher-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> On Thu, Jan 12, 2017 at 2:41 AM, Monk Liu <Monk.Liu-5C7GfCeVMHo@public.gmane.org> wro= te:
>> ce's META-DATA write need prior to cntx_cntrl package
>> and de's should following.
>>
>> Change-Id: I2bf436d8a16bae38ce484f846f0b399e16cfe80a
>> Signed-off-by: Monk Liu <Monk.Liu-5C7GfCeVMHo@public.gmane.org>
>
> Reviewed-by: Alex Deucher <alexander.deucher-5C7GfCeVMHo@public.gmane.org>
Actually, I take that back.  A few comments below.

>
>> ---
>>  drivers/gpu/drm/amd/amdgpu/amdgpu.h    | 1 &#= 43;
>>  drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 3 +++ >>  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c  | 8 ++&#= 43;+++++
>>  3 files changed, 12 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm= /amd/amdgpu/amdgpu.h
>> index 2039da7..b7f7679 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> @@ -953,6 +953,7 @@ struct amdgpu_cs_parser {
>>  #define AMDGPU_PREAMBLE_IB_PRESENT    &n= bsp;     (1 << 0) /* bit set means command submit= involves a preamble IB */
>>  #define AMDGPU_PREAMBLE_IB_PRESENT_FIRST    (= 1 << 1) /* bit set means preamble IB is first presented in belonging = context */
>>  #define AMDGPU_HAVE_CTX_SWITCH     =          (1 << 2) /* bit set = means context switch occured */
>> +#define AMDGPU_VM_DOMAIN      &= nbsp;           &nbs= p; (1 << 3) /* bit set means in virtual memory context */
>>
>>  struct amdgpu_job {
>>         struct amd_sched_j= ob    base;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/= drm/amd/amdgpu/amdgpu_ib.c
>> index 16308eb..6939822 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
>> @@ -184,6 +184,9 @@ int amdgpu_ib_schedule(struct amdgpu_ring = *ring, unsigned num_ibs,
>>           &= nbsp;     if (need_ctx_switch)
>>           &= nbsp;           &nbs= p; status |=3D AMDGPU_HAVE_CTX_SWITCH;
>>           &= nbsp;     status |=3D job->preamble_status;
>> +
>> +          &= nbsp;    if (vm)
>> +          &= nbsp;            sta= tus |=3D AMDGPU_VM_DOMAIN;
>>           &= nbsp;     amdgpu_ring_emit_cntxcntl(ring, status);
>>         }
>>

This top chunk should be a separate patch.


>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/d= rm/amd/amdgpu/gfx_v8_0.c
>> index 3e8cff3..8a5c818 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
>> @@ -6704,6 +6704,10 @@ static void gfx_v8_ring_emit_cntxcntl(s= truct amdgpu_ring *ring, uint32_t flags)
>>  {
>>         uint32_t dw2 =3D 0= ;
>>
>> +       if (amdgpu_sriov_vf(ring= ->adev))
>> +          &= nbsp;    gfx_v8_0_ring_emit_ce_meta_init(ring,
>> +          &= nbsp;            (fl= ags & AMDGPU_VM_DOMAIN) ? AMDGPU_CSA_VADDR : ring->adev->virt.csa= _vmid0_addr);
>> +
>>         dw2 |=3D 0x8000000= 0; /* set load_enable otherwise this package is just NOPs */
>>         if (flags & AM= DGPU_HAVE_CTX_SWITCH) {
>>           &= nbsp;     gfx_v8_0_ring_emit_vgt_flush(ring);
>> @@ -6728,6 +6732,10 @@ static void gfx_v8_ring_emit_cntxcntl(s= truct amdgpu_ring *ring, uint32_t flags)
>>         amdgpu_ring_write(= ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
>>         amdgpu_ring_write(= ring, dw2);
>>         amdgpu_ring_write(= ring, 0);
>> +
>> +       if (amdgpu_sriov_vf(ring= ->adev))
>> +          &= nbsp;    gfx_v8_0_ring_emit_de_meta_init(ring,
>> +          &= nbsp;            (fl= ags & AMDGPU_VM_DOMAIN) ? AMDGPU_CSA_VADDR : ring->adev->virt.csa= _vmid0_addr);
>>  }
>>

I think you need to update the emit_frame_size to reflect the larger frame.=

>>  static void gfx_v8_0_set_gfx_eop_interrupt_state(struct amdg= pu_device *adev,
>> --
>> 2.7.4
>>
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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