From mboxrd@z Thu Jan  1 00:00:00 1970
From: Tan, Ley Foon <ley.foon.tan@intel.com>
Date: Mon, 6 Apr 2020 08:57:12 +0000
Subject: [PATCH v1 1/2] clk: socfpga: Read the clock parent's register
 base in probe function
In-Reply-To: <20200403122114.GW27133@bill-the-cat>
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> -----Original Message-----
> From: Tom Rini <trini@konsulko.com>
> Sent: Friday, April 3, 2020 8:21 PM
> To: Tan, Ley Foon <ley.foon.tan@intel.com>
> Cc: Marek Vasut <marex@denx.de>; Simon Glass <sjg@chromium.org>; Ang,
> Chee Hong <chee.hong.ang@intel.com>; U-Boot Mailing List <u-
> boot at lists.denx.de>; Simon Goldschmidt
> <simon.k.r.goldschmidt@gmail.com>; See, Chin Liang
> <chin.liang.see@intel.com>; Westergreen, Dalon
> <dalon.westergreen@intel.com>
> Subject: Re: [PATCH v1 1/2] clk: socfpga: Read the clock parent's register
> base in probe function
> 
> On Fri, Apr 03, 2020 at 03:52:54AM +0000, Tan, Ley Foon wrote:
> >
> >
> > > -----Original Message-----
> > > From: Marek Vasut <marex@denx.de>
> > > Sent: Friday, April 3, 2020 6:47 AM
> > > To: Tom Rini <trini@konsulko.com>
> > > Cc: Simon Glass <sjg@chromium.org>; Ang, Chee Hong
> > > <chee.hong.ang@intel.com>; U-Boot Mailing List
> > > <u-boot@lists.denx.de>; Simon Goldschmidt
> > > <simon.k.r.goldschmidt@gmail.com>; See, Chin Liang
> > > <chin.liang.see@intel.com>; Tan, Ley Foon <ley.foon.tan@intel.com>;
> > > Westergreen, Dalon <dalon.westergreen@intel.com>
> > > Subject: Re: [PATCH v1 1/2] clk: socfpga: Read the clock parent's
> > > register base in probe function
> > >
> > > On 4/3/20 12:10 AM, Tom Rini wrote:
> > > > On Thu, Apr 02, 2020 at 11:07:31PM +0200, Marek Vasut wrote:
> > > >> On 4/2/20 10:54 PM, Tom Rini wrote:
> > > >> [...]
> > > >>
> > > >>>>>>>> I'm not sure it definitely should be changed. But I'll do a
> > > >>>>>>>> patch and see how it looks.
> > > >>>>>>>
> > > >>>>>>> Do I understand it correctly that the patch
> > > >>>>>>> 82de42fa14682d408da935adfb0f935354c5008f actually
> completely
> > > >>>>>>> breaks SoCFPGA ? Then I would say this is a release blocker ?
> > > >>>>>> Yes. A10 SPL won't boot at all. It crashes during the clock
> > > >>>>>> manager
> > > setup.
> > > >>>>>
> > > >>>>> This came in right at the beginning of the cycle. I thought
> > > >>>>> the purpose of the 3-month cycle was to allow time to test?
> > > >>>>
> > > >>>> It was ... altera ?
> > > >>>
> > > >>> Sorry, I'm missing how that's an answer to the question.  This
> > > >>> came in basically right at the start of the merge window.
> > > >>
> > > >> I don't have an A10 available right now, so what can I do ?
> > > >
> > > > Ah, so the answer is "I can't test this platform myself".  That's
> > > > what then, thanks.
> > >
> > > Clearly Altera can , since they reported this issue.
> > Yes, we have Arria10 devkit here and we see the issue when testing latest
> uboot.
> > It looks like other platform [1] also encounter issue with patch
> 82de42fa14682d40. Like Marek said, we don't know any other driver is
> broken after this patch.
> >
> > [1] https://patchwork.ozlabs.org/patch/1265188/
> 
> Yes, my concern here is that the platform in question wasn't tested after -rc1
> or -rc2 or -rc3 only right now just before release.  So we're in a bit of a
> scramble to fix the driver.  Thanks!
> 
We will improve our regression test going forward. Sorry about that.

Thanks.

Regards
Ley Foon