From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by smtp.lore.kernel.org (Postfix) with ESMTP id 11A37C433EF for ; Tue, 31 May 2022 18:59:12 +0000 (UTC) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E5E3140A87; Tue, 31 May 2022 20:59:11 +0200 (CEST) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mails.dpdk.org (Postfix) with ESMTP id 7B12A40A84 for ; Tue, 31 May 2022 20:59:09 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1654023549; x=1685559549; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=dQDcr2xSDZv8h9xLOIkaB/WDaipxxpt7m9Hk1CFvMVM=; b=Jt0wECgtD2T6BumGb8+GIDDLvFsNlC11dB+hHM1PhNSvEVUkjSSNfAHn wMP6XxpCzZH+q7tumB/Wu6SwrJgyYTCVhb31hut1ZZLi9kwo93OD5j108 jrvSWfNJFF13UwT0esenzyCK1c5DPzN5Gn0zSgCES3M7kC9fNYDcQ/E1H RqJ9O+8bWmzq/uf9Tx3yh4QXc3M0MkrNy42Gg6TvLqLpt9AMkQ70z6Oyg qQx/vgWB7zTpnc5W+GjKvK29mulUb5G37LVoxo9hplUjG+OI/yp0Kr3G+ Ik+rLKTDUkaOJUGG8Z2UxLY2RAbCTVFEHs+PlQczcVAafMDP8T703kPeD g==; X-IronPort-AV: E=McAfee;i="6400,9594,10364"; a="257423127" X-IronPort-AV: E=Sophos;i="5.91,266,1647327600"; d="scan'208";a="257423127" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 May 2022 11:59:07 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,266,1647327600"; d="scan'208";a="823405457" Received: from orsmsx601.amr.corp.intel.com ([10.22.229.14]) by fmsmga006.fm.intel.com with ESMTP; 31 May 2022 11:59:06 -0700 Received: from orsmsx611.amr.corp.intel.com (10.22.229.24) by ORSMSX601.amr.corp.intel.com (10.22.229.14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.27; Tue, 31 May 2022 11:59:05 -0700 Received: from ORSEDG602.ED.cps.intel.com (10.7.248.7) by orsmsx611.amr.corp.intel.com (10.22.229.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.27 via Frontend Transport; Tue, 31 May 2022 11:59:05 -0700 Received: from NAM02-SN1-obe.outbound.protection.outlook.com (104.47.57.41) by edgegateway.intel.com (134.134.137.103) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2308.27; Tue, 31 May 2022 11:59:05 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=A3Q+Y07PGs6boW8Q+8eWOcOuZGPkEB/5T96QqNboShbiq2XXBSbKpliLiAcHUOnoWCnkf+0hqQZe9TvRYhlSukknF27FEvbH/xyGaV9EGML6cMpyjXqrV4DFax0TJBfh5Bqx603GOQucEfvJuY0B1wBs21TS0+kl0t1uVUrAl+fTJNj/c0RPgLrqZ3nuMO7tAoqNc8uEhxRdESZTWJNOkNeruytjUjYeCnOptzKnuIo3SBOAa/ewgB+Y2v8laKV4eY94OYokz+rh9jQ9paIemB7e1/GZHHfIc4pQJHqzLBAm0t3qXLRshY7Lf8inR2PcTdypd8niYzTYm0nq6hcpUA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=HAcU/Ds3AQwspxDLa8Dm8rybA+1E8aiIhsKfsUAm8Us=; b=KtQoNSbRKKTeh01fxwEYTj8AwXDT8SN48dEoGtJEi+L8E11Igeytb0ZJvvXoapSwz+HugZZ10sv/cZJu4rjbT8iUiXRd3wSH3KAKRYvTRCyLzUgtIrDFgY7lXHuxVU70XgVjR59ryAJ3MvuO8YQRtBHZ39Ai5mFT5rZER00NvX8JU6cJcTHdhzrUvdnuaCbcGkiHY+sCL33GjuOjULKT086sM9M5tOiuDptsIzZLb7RkzMXVzejbpsY+J4jmBCm/jGHjuCDhKWT+bxRGf9SHCx03hiWFdNbHeLLIobK8RA0Jn3DuU937oKVfmHz3vA9SkTLbvJSIvang9yW3HzRS5Q== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Received: from BY5PR11MB4451.namprd11.prod.outlook.com (2603:10b6:a03:1cb::30) by SN6PR11MB3325.namprd11.prod.outlook.com (2603:10b6:805:b7::30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5293.13; Tue, 31 May 2022 18:59:02 +0000 Received: from BY5PR11MB4451.namprd11.prod.outlook.com ([fe80::40f:170c:c586:7219]) by BY5PR11MB4451.namprd11.prod.outlook.com ([fe80::40f:170c:c586:7219%2]) with mapi id 15.20.5293.019; Tue, 31 May 2022 18:59:02 +0000 From: "Chautru, Nicolas" To: Akhil Goyal , "dev@dpdk.org" , "trix@redhat.com" , "maxime.coquelin@redhat.com" CC: "thomas@monjalon.net" , "Kinsella, Ray" , "Richardson, Bruce" , "hemant.agrawal@nxp.com" , "Vargas, Hernan" , "david.marchand@redhat.com" Subject: RE: [EXT] [PATCH v6 3/5] baseband/acc100: introduce PMD for ACC101 Thread-Topic: [EXT] [PATCH v6 3/5] baseband/acc100: introduce PMD for ACC101 Thread-Index: AQHYcJyNYXg/soRwkkiM52Xa+72hpK03D8EAgAJHdxA= Date: Tue, 31 May 2022 18:59:02 +0000 Message-ID: References: <1653350912-53876-1-git-send-email-nicolas.chautru@intel.com> <1653526523-68839-1-git-send-email-nicolas.chautru@intel.com> <1653526523-68839-4-git-send-email-nicolas.chautru@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.6.500.17 authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 31e7e95e-b825-4c4b-6e1e-08da4337a0ca x-ms-traffictypediagnostic: SN6PR11MB3325:EE_ x-ld-processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr x-microsoft-antispam-prvs: x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: 1sxFlR5XcLPFR57Bi8y0iGaE/NSviCt/lFKrRLXil4Mpb4IJJIU2H3GxO7CJmjH6pxyFvQh5Ty1Mje1UT0479Sf5Nc/pltikJzIa6gG2RY3/FryOPsHzyKRLBbY8q9sQOvzua84eUk/KfIh2xUFQ6hoWsF2aAX5BSUFJTNqg3d9q9dWmf8YyIV64KfqQmonml2pIUhW4Y9yRz2lsp861XEbUYm2PeKmQYZfvShqMQ1DnYrCzQbFjVjxbudGlGSXkoEgjOxXFd2UIY/+tkYKpAOGGnvL68rkjF0s89rPLp+HgtLgBZzeHKspgNGDThk66atnTGA5z/4xEsmkNKuNLlXhusYBrbonW1xDLl8kPTajKl2MyFbQxp7GENtqM0ABWAiIjAeLse5SPnJ4CBHcla85mmBBbzA46uu4l2SizlrbDRg9fKnebDeVcuCUZo4b9ZJid+43MdQzx1EPqqy9pnDVrlvv52xujKY+u5eXywF8Iw9wvK/b08IP9a7mTOsAdqd4T/NBP1oHJna+98ehZfvMc7/Ij4HP6snG5lYXjPlU3lHXkqB42NHlW2DwNwPZfdNSVtN+vR7dWnpRTwG7Y9K5R8pXO6L8IqSd71zeJv8i3y0bUrBKf4PhPdt/UtrnP2zMOn3TAOP/kXURqCrJkQFnZs1p3tue/L+hu5Ow8LKQgbnQaT7YsyDpqB3BbIAW+aYUDpfUG1Tp1yfA8h7V2QA== x-forefront-antispam-report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:BY5PR11MB4451.namprd11.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230001)(366004)(55016003)(38100700002)(186003)(64756008)(54906003)(110136005)(316002)(4326008)(8676002)(66476007)(66556008)(66946007)(66446008)(76116006)(83380400001)(38070700005)(8936002)(508600001)(71200400001)(6506007)(86362001)(7696005)(52536014)(53546011)(5660300002)(33656002)(30864003)(82960400001)(122000001)(26005)(9686003)(2906002); DIR:OUT; SFP:1102; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?pshnCYCD+KYP4VhQ/Hls9Br4bcSGKVenNhJ6lgmQ1QtxdOqVgRRilsXgIcau?= =?us-ascii?Q?QYp/S2ouxtIPHFzh8W97IJ7RfCb2QsJuWs8AkdzulInZUh4b7NDjpf/uTvWy?= =?us-ascii?Q?TizsMBMI/GlAnh1N6of9qpfapN19Upeyih+vnGt0v+xZSkuLWA42GqWCTk7w?= =?us-ascii?Q?yMxU3fdEWU5UXp4sDW4V3fbNMbcj8GLGDWbvMA5k47rcZqUpAdiX8/aD7kiW?= =?us-ascii?Q?SHvSkaHZsEM354izr8g1ZLvuVphujPnngFiZWKbfZYCTiKUyJGFr+x586sDB?= =?us-ascii?Q?9etmtRhV21aUElCkhjNfr8u/QzmPAS2aR0uVEWo5FG+6XHP2j0HYKiELjqz3?= =?us-ascii?Q?LPjNpd/tqsTfr2GJNM1tGQWitLSibEoasvcLCpOp76F43ua3qzUIDj++vW3v?= =?us-ascii?Q?ckp6QkszBgWRsveScQugt6Hz+MH2/979I65YgvKigtBMQa4jf6DY9CWR74wp?= =?us-ascii?Q?Ew9KgNzI8ufiY590L4Yuq/Mjc4OGQKaU97lgJTwN5vVcp4jXYeAK9NBKe4E7?= =?us-ascii?Q?AToMRuPzrxhqR74lIdCXDzf0n4JUGWnYETmXHdoRiE/3nrLgwSSok/0jecJj?= =?us-ascii?Q?sXj/CTz3TdvF9uwS5vXQs4vYJfPjhFebKFVMtW2ortlFpWBpqvq3nWmXtQ1u?= =?us-ascii?Q?A8HUch0uckc+0ZlZXly+QC1yQku5EUeYduIwuYZvCAWEqPIhRwQrS3BMYvDW?= =?us-ascii?Q?mdr8mfVzGyOVVae/VBJSqesNY+kNSF5j4MARYfwBDgXONa9IAoTHC/ERX1qu?= =?us-ascii?Q?Qbg2TCTNkk+u3+Npi4d1JQ4fmY5Deji4gRBquWg0ut+A2c4WUqwRO81x7kwM?= =?us-ascii?Q?qHamkCqSfO3pucN9fRTYau2O4Qq4r6+JSE/iqkXa+T6fQXHc5nt7b+4U1yuZ?= =?us-ascii?Q?Up3U2R0LDPQoRRymAAr40KfeY3auhBOOmvHRF29b8Z5SHgw2kau/9cRRveH8?= =?us-ascii?Q?wYjEUZ7AXOjmd7Ytuz11UmFmUXgtCcfiGgvthDBI6ug/auge6hoaC7hZSeS2?= =?us-ascii?Q?uAAc3MJ8L2X9iGFRKDNNLNgqzPNLZI/eXohdnynDya1NZYy5qar5rf1lxoPR?= =?us-ascii?Q?ktWW2etUIl8g3hnOQfGpQLKpJ+OvApYPWcUahVGvCwmDVpaeEUjgYiB1lHJa?= =?us-ascii?Q?ha38PUEclqa845NS3Pf3AHE1d7sz38gzqWa0M+Os7CNCmeYsnL+e+20hW4p1?= =?us-ascii?Q?MgjlBK0DHOsMNAum/gNGAC6zbCBBE+l0eeav3u/se3bCcV+gucGKr8G4fYsT?= =?us-ascii?Q?1pSTy57HTUqc3iOV1rVf7deyraaLbpSViQyARLzW+YjHH4UedfY3Sbntu83o?= =?us-ascii?Q?UdbKPHblJ4hC1+1Mt8rJWpGNj6BSexkpT9vmjhaJLFVCTbGd+w6xhZXZbbmr?= =?us-ascii?Q?Fc8OiH8pbtrNVYhjgnQ0iB3HAMBHNDt+2RS1fAvnI65HfOkN15pAPv5s/9o0?= =?us-ascii?Q?JhbUh675l8hZIq65prCLv/TLOORnKEQlQIafg+9gkN7ic0MwDBf+4i8RNpWW?= =?us-ascii?Q?LUXsRdK5pcB2EaRUD0ItmQCJd0qIECmbRybvEogQkveH10YR1/Shs4d1Zy25?= =?us-ascii?Q?u90+D/o+sd5lrt/3bXRZP+J9AxSkUbkcWcym6pJk4s3OcEYOdB0i6+8yl4KC?= =?us-ascii?Q?Vsqv5uXr6ysqEb3645IXo6uh1F2eTxUi2QZQ4eMAwuGHnayuJlrAtcygxxUt?= =?us-ascii?Q?J0s0Fn1Lug/S2kpKg+BD+QQhADJGsbQdKmqEW8G1ael+vCETmZQSgFmitXbO?= =?us-ascii?Q?0HK0v31iuVUHafmPsPFfDceQ4dD1nfg=3D?= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BY5PR11MB4451.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 31e7e95e-b825-4c4b-6e1e-08da4337a0ca X-MS-Exchange-CrossTenant-originalarrivaltime: 31 May 2022 18:59:02.5604 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: b8XvQSpxIqW0yTM2AAAIZlNMGNnYAxfAxOnf9maAs3TUPwk9MvufOF9h6nzsf2c1qYGfiT4oQ2T1PxFXIWoaS5aWB6AOAda/HJILQyvZg4I= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR11MB3325 X-OriginatorOrg: intel.com X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Hi Akhil,=20 > -----Original Message----- > From: Akhil Goyal > Sent: Monday, May 30, 2022 12:40 AM > To: Chautru, Nicolas ; dev@dpdk.org; > trix@redhat.com; maxime.coquelin@redhat.com > Cc: thomas@monjalon.net; Kinsella, Ray ; > Richardson, Bruce ; > hemant.agrawal@nxp.com; Vargas, Hernan ; > david.marchand@redhat.com > Subject: RE: [EXT] [PATCH v6 3/5] baseband/acc100: introduce PMD for > ACC101 >=20 > > > > > > Enable Virtual Functions > > @@ -167,14 +172,14 @@ queues, priorities, load balance, bandwidth and > > other settings necessary for the device to perform FEC functions. > > > > This configuration needs to be executed at least once after reboot or > > PCI FLR and can -be achieved by using the function > > ``acc100_configure()``, which sets up the -parameters defined in > > ``acc100_conf`` structure. > > +be achieved by using the functions ``acc100_configure()`` or > > ``acc101_configure()``, >=20 > I believe the API for user is common now. Right? So why to have two > references? Thanks, I will amend the documentation now.=20 >=20 > > +which sets up the parameters defined in the compatible > > +``acc100_conf`` > > structure. > > > > Test Application > > ---------------- > > > > BBDEV provides a test application, ``test-bbdev.py`` and range of > > test data for testing -the functionality of ACC100 5G/4G FEC encode > > and decode, depending on the device's > > +the functionality of the device 5G/4G FEC encode and decode, > > +depending on > > the device's > > capabilities. The test application is located under app->test-bbdev > > folder and has the following options: > > > > @@ -212,7 +217,7 @@ Test Vectors > > > > In addition to the simple LDPC decoder and LDPC encoder tests, bbdev > > also provides a range of additional tests under the test_vectors > > folder, which may be useful. > > The results > > -of these tests will depend on the ACC100 5G/4G FEC capabilities which > > may cause some > > +of these tests will depend on the device 5G/4G FEC capabilities which > > +may > > cause some > > testcases to be skipped, but no failure should be reported. > > > > > > @@ -233,3 +238,11 @@ Specifically for the BBDEV ACC100 PMD, the > > command below can be used: > > > > ./pf_bb_config ACC100 -c acc100/acc100_config_vf_5g.cfg > > ./test-bbdev.py -e=3D"-c 0xff0 -a${VF_PCI_ADDR}" -c validation -n 64 > > -b 32 -l 1 -v ./ldpc_dec_default.data > > + > > +Specifically for the BBDEV ACC101 PMD, the command below can be used: > > + > > +.. code-block:: console > > + > > + ./pf_bb_config ACC101 -c acc101/acc101_config_2vf_4g5g.cfg > > + ./test-bbdev.py -e=3D"-c 0xff0 -a${VF_PCI_ADDR}" -c validation -n 64 > > + -b 32 -l 1 - > > v ./ldpc_dec_default.data > > + > > diff --git a/doc/guides/bbdevs/features/acc101.ini > > b/doc/guides/bbdevs/features/acc101.ini > > new file mode 100644 > > index 0000000..0e2c21a > > --- /dev/null > > +++ b/doc/guides/bbdevs/features/acc101.ini > > @@ -0,0 +1,13 @@ > > +; > > +; Supported features of the 'acc101' bbdev driver. > > +; > > +; Refer to default.ini for the full list of available PMD features. > > +; > > +[Features] > > +Turbo Decoder (4G) =3D Y > > +Turbo Encoder (4G) =3D Y > > +LDPC Decoder (5G) =3D Y > > +LDPC Encoder (5G) =3D Y > > +LLR/HARQ Compression =3D Y > > +External DDR Access =3D Y > > +HW Accelerated =3D Y > > diff --git a/doc/guides/rel_notes/release_22_07.rst > > b/doc/guides/rel_notes/release_22_07.rst > > index e49cace..1803947 100644 > > --- a/doc/guides/rel_notes/release_22_07.rst > > +++ b/doc/guides/rel_notes/release_22_07.rst > > @@ -104,6 +104,9 @@ New Features > > * ``RTE_EVENT_QUEUE_ATTR_WEIGHT`` > > * ``RTE_EVENT_QUEUE_ATTR_AFFINITY`` > > > > +* **Added Intel ACC101 baseband PMD.** > > + > > + * Added a new baseband PMD for Intel ACC101 device. > > > > Removed Items > > ------------- > > diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c > > b/drivers/baseband/acc100/rte_acc100_pmd.c > > index 3fdf17d..6a2123b 100644 > > --- a/drivers/baseband/acc100/rte_acc100_pmd.c > > +++ b/drivers/baseband/acc100/rte_acc100_pmd.c > > @@ -22,6 +22,7 @@ > > #include > > #include > > #include "rte_acc100_pmd.h" > > +#include "rte_acc101_pmd.h" > > > > #ifdef RTE_LIBRTE_BBDEV_DEBUG > > RTE_LOG_REGISTER_DEFAULT(acc100_logtype, DEBUG); @@ -1133,7 > +1134,10 > > @@ > > /* ACC100 PCI PF address map */ > > static struct rte_pci_id pci_id_acc100_pf_map[] =3D { > > { > > - RTE_PCI_DEVICE(RTE_ACC100_VENDOR_ID, > > RTE_ACC100_PF_DEVICE_ID) > > + RTE_PCI_DEVICE(RTE_ACC100_VENDOR_ID, > > RTE_ACC100_PF_DEVICE_ID), > > + }, > > + { > > + RTE_PCI_DEVICE(RTE_ACC101_VENDOR_ID, > > RTE_ACC101_PF_DEVICE_ID), > > }, > > {.device_id =3D 0}, > > }; > > @@ -1141,7 +1145,10 @@ > > /* ACC100 PCI VF address map */ > > static struct rte_pci_id pci_id_acc100_vf_map[] =3D { > > { > > - RTE_PCI_DEVICE(RTE_ACC100_VENDOR_ID, > > RTE_ACC100_VF_DEVICE_ID) > > + RTE_PCI_DEVICE(RTE_ACC100_VENDOR_ID, > > RTE_ACC100_VF_DEVICE_ID), > > + }, > > + { > > + RTE_PCI_DEVICE(RTE_ACC101_VENDOR_ID, > > RTE_ACC101_VF_DEVICE_ID), > > }, > > {.device_id =3D 0}, > > }; > > @@ -1290,7 +1297,7 @@ > > > > /* Fill in a frame control word for LDPC decoding. */ static inline > > void -acc100_fcw_ld_fill(const struct rte_bbdev_dec_op *op, struct > > acc100_fcw_ld *fcw, > > +acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld > > +*fcw, > > union acc100_harq_layout_data *harq_layout) { > > uint16_t harq_out_length, harq_in_length, ncb_p, k0_p, > > parity_offset; @@ -1414,6 +1421,128 @@ > > } > > } > > > > +/* Convert offset to harq index for harq_layout structure */ static > > +inline uint32_t hq_index(uint32_t offset) { > > + return (offset >> ACC100_HARQ_OFFSET_SHIFT) & > > ACC100_HARQ_OFFSET_MASK; > > +} > > + > > +/* Fill in a frame control word for LDPC decoding for ACC101 */ > > +static inline void acc101_fcw_ld_fill(struct rte_bbdev_dec_op *op, > > +struct acc100_fcw_ld *fcw, > > + union acc100_harq_layout_data *harq_layout) { > > + uint16_t harq_out_length, harq_in_length, ncb_p, k0_p, > parity_offset; > > + uint32_t harq_index; > > + uint32_t l; > > + > > + fcw->qm =3D op->ldpc_dec.q_m; > > + fcw->nfiller =3D op->ldpc_dec.n_filler; > > + fcw->BG =3D (op->ldpc_dec.basegraph - 1); > > + fcw->Zc =3D op->ldpc_dec.z_c; > > + fcw->ncb =3D op->ldpc_dec.n_cb; > > + fcw->k0 =3D get_k0(fcw->ncb, fcw->Zc, op->ldpc_dec.basegraph, > > + op->ldpc_dec.rv_index); > > + if (op->ldpc_dec.code_block_mode =3D=3D RTE_BBDEV_CODE_BLOCK) > > + fcw->rm_e =3D op->ldpc_dec.cb_params.e; > > + else > > + fcw->rm_e =3D (op->ldpc_dec.tb_params.r < > > + op->ldpc_dec.tb_params.cab) ? > > + op->ldpc_dec.tb_params.ea : > > + op->ldpc_dec.tb_params.eb; > > + > > + if (unlikely(check_bit(op->ldpc_dec.op_flags, > > + RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE) && > > + (op->ldpc_dec.harq_combined_input.length =3D=3D 0))) { > > + rte_bbdev_log(WARNING, "Null HARQ input size provided"); > > + /* Disable HARQ input in that case to carry forward */ > > + op->ldpc_dec.op_flags ^=3D > > RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE; > > + } > > + > > + fcw->hcin_en =3D check_bit(op->ldpc_dec.op_flags, > > + RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE); > > + fcw->hcout_en =3D check_bit(op->ldpc_dec.op_flags, > > + RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE); > > + fcw->crc_select =3D check_bit(op->ldpc_dec.op_flags, > > + RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK); > > + fcw->bypass_dec =3D check_bit(op->ldpc_dec.op_flags, > > + RTE_BBDEV_LDPC_DECODE_BYPASS); > > + fcw->bypass_intlv =3D check_bit(op->ldpc_dec.op_flags, > > + RTE_BBDEV_LDPC_DEINTERLEAVER_BYPASS); > > + if (op->ldpc_dec.q_m =3D=3D 1) { > > + fcw->bypass_intlv =3D 1; > > + fcw->qm =3D 2; > > + } > > + fcw->hcin_decomp_mode =3D check_bit(op->ldpc_dec.op_flags, > > + RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION); > > + fcw->hcout_comp_mode =3D check_bit(op->ldpc_dec.op_flags, > > + RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION); > > + fcw->llr_pack_mode =3D check_bit(op->ldpc_dec.op_flags, > > + RTE_BBDEV_LDPC_LLR_COMPRESSION); > > + harq_index =3D hq_index(op- > >ldpc_dec.harq_combined_output.offset); > > + if (fcw->hcin_en > 0) { > > + harq_in_length =3D op- > >ldpc_dec.harq_combined_input.length; > > + if (fcw->hcin_decomp_mode > 0) > > + harq_in_length =3D harq_in_length * 8 / 6; > > + harq_in_length =3D RTE_MIN(harq_in_length, op- > >ldpc_dec.n_cb > > + - op->ldpc_dec.n_filler); > > + /* Alignment on next 64B - Already enforced from HC output > */ > > + harq_in_length =3D RTE_ALIGN_FLOOR(harq_in_length, 64); > > + fcw->hcin_size0 =3D harq_in_length; > > + fcw->hcin_offset =3D 0; > > + fcw->hcin_size1 =3D 0; > > + } else { > > + fcw->hcin_size0 =3D 0; > > + fcw->hcin_offset =3D 0; > > + fcw->hcin_size1 =3D 0; > > + } > > + > > + fcw->itmax =3D op->ldpc_dec.iter_max; > > + fcw->itstop =3D check_bit(op->ldpc_dec.op_flags, > > + RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE); > > + fcw->synd_precoder =3D fcw->itstop; > > + /* > > + * These are all implicitly set > > + * fcw->synd_post =3D 0; > > + * fcw->so_en =3D 0; > > + * fcw->so_bypass_rm =3D 0; > > + * fcw->so_bypass_intlv =3D 0; > > + * fcw->dec_convllr =3D 0; > > + * fcw->hcout_convllr =3D 0; > > + * fcw->hcout_size1 =3D 0; > > + * fcw->so_it =3D 0; > > + * fcw->hcout_offset =3D 0; > > + * fcw->negstop_th =3D 0; > > + * fcw->negstop_it =3D 0; > > + * fcw->negstop_en =3D 0; > > + * fcw->gain_i =3D 1; > > + * fcw->gain_h =3D 1; > > + */ > > + if (fcw->hcout_en > 0) { > > + parity_offset =3D (op->ldpc_dec.basegraph =3D=3D 1 ? 20 : 8) > > + * op->ldpc_dec.z_c - op->ldpc_dec.n_filler; > > + k0_p =3D (fcw->k0 > parity_offset) ? > > + fcw->k0 - op->ldpc_dec.n_filler : fcw->k0; > > + ncb_p =3D fcw->ncb - op->ldpc_dec.n_filler; > > + l =3D RTE_MIN(k0_p + fcw->rm_e, INT16_MAX); > > + harq_out_length =3D (uint16_t) fcw->hcin_size0; > > + harq_out_length =3D RTE_MAX(harq_out_length, l); > > + /* Cannot exceed the pruned Ncb circular buffer */ > > + harq_out_length =3D RTE_MIN(harq_out_length, ncb_p); > > + /* Alignment on next 64B */ > > + harq_out_length =3D RTE_ALIGN_CEIL(harq_out_length, 64); > > + fcw->hcout_size0 =3D harq_out_length; > > + fcw->hcout_size1 =3D 0; > > + fcw->hcout_offset =3D 0; > > + harq_layout[harq_index].offset =3D fcw->hcout_offset; > > + harq_layout[harq_index].size0 =3D fcw->hcout_size0; > > + } else { > > + fcw->hcout_size0 =3D 0; > > + fcw->hcout_size1 =3D 0; > > + fcw->hcout_offset =3D 0; > > + } > > +} > > + > > /** > > * Fills descriptor with data pointers of one block type. > > * > > @@ -2966,7 +3095,7 @@ > > struct acc100_fcw_ld *fcw; > > uint32_t seg_total_left; > > fcw =3D &desc->req.fcw_ld; > > - acc100_fcw_ld_fill(op, fcw, harq_layout); > > + q->d->fcw_ld_fill(op, fcw, harq_layout); > > > > /* Special handling when overusing mbuf */ > > if (fcw->rm_e < ACC100_MAX_E_MBUF) > > @@ -3033,7 +3162,7 @@ > > desc =3D q->ring_addr + desc_idx; > > uint64_t fcw_offset =3D (desc_idx << 8) + ACC100_DESC_FCW_OFFSET; > > union acc100_harq_layout_data *harq_layout =3D q->d->harq_layout; > > - acc100_fcw_ld_fill(op, &desc->req.fcw_ld, harq_layout); > > + q->d->fcw_ld_fill(op, &desc->req.fcw_ld, harq_layout); > > > > input =3D op->ldpc_dec.input.data; > > h_output_head =3D h_output =3D op->ldpc_dec.hard_output.data; @@ - > 4145,9 > > +4274,19 @@ > > dev->dequeue_ldpc_enc_ops =3D acc100_dequeue_ldpc_enc; > > dev->dequeue_ldpc_dec_ops =3D acc100_dequeue_ldpc_dec; > > > > + /* Device variant specific handling */ > > + if ((pci_dev->id.device_id =3D=3D RTE_ACC100_PF_DEVICE_ID) || > > + (pci_dev->id.device_id =3D=3D > RTE_ACC100_VF_DEVICE_ID)) > > { > > + ((struct acc100_device *) dev->data->dev_private)- > > >device_variant =3D ACC100_VARIANT; > > + ((struct acc100_device *) dev->data->dev_private)- > >fcw_ld_fill > > =3D acc100_fcw_ld_fill; > > + } else { > > + ((struct acc100_device *) dev->data->dev_private)- > > >device_variant =3D ACC101_VARIANT; > > + ((struct acc100_device *) dev->data->dev_private)- > >fcw_ld_fill > > =3D acc101_fcw_ld_fill; > > + } > > + > > ((struct acc100_device *) dev->data->dev_private)->pf_device =3D > > - !strcmp(drv->driver.name, > > - RTE_STR(ACC100PF_DRIVER_NAME)); > > + !strcmp(drv->driver.name, > > RTE_STR(ACC100PF_DRIVER_NAME)); > > + > > ((struct acc100_device *) dev->data->dev_private)->mmio_base =3D > > pci_dev->mem_resource[0].addr; > > > > diff --git a/drivers/baseband/acc100/rte_acc100_pmd.h > > b/drivers/baseband/acc100/rte_acc100_pmd.h > > index 8fea322..39d5f22 100644 > > --- a/drivers/baseband/acc100/rte_acc100_pmd.h > > +++ b/drivers/baseband/acc100/rte_acc100_pmd.h > > @@ -22,6 +22,9 @@ > > #define rte_bbdev_log_debug(fmt, ...) #endif > > > > +#define ACC100_VARIANT 0 > > +#define ACC101_VARIANT 1 >=20 > Since you are using PCI dev id for identifying the device. Do we still ne= ed > above defines? The implementation is_acc100() is based on checking that enum=20 (q->d->device_variant =3D=3D ACC100_VARIANT); > > + > > /* ACC100 PF and VF driver names */ > > #define ACC100PF_DRIVER_NAME intel_acc100_pf > > #define ACC100VF_DRIVER_NAME intel_acc100_vf > > @@ -67,6 +70,8 @@ > > #define ACC100_HARQ_LAYOUT (64*1024*1024) > > /* Assume offset for HARQ in memory */ > > #define ACC100_HARQ_OFFSET (32*1024) > > +#define ACC100_HARQ_OFFSET_SHIFT 15 > > +#define ACC100_HARQ_OFFSET_MASK 0x7ffffff > > /* Mask used to calculate an index in an Info Ring array (not a byte o= ffset) > */ > > #define ACC100_INFO_RING_MASK > (ACC100_INFO_RING_NUM_ENTRIES- > > 1) > > /* Number of Virtual Functions ACC100 supports */ @@ -574,6 +579,10 > > @@ struct __rte_cache_aligned acc100_queue { > > struct acc100_device *d; > > }; > > > > +typedef void (*acc10x_fcw_ld_fill_fun_t)(struct rte_bbdev_dec_op *op, > > + struct acc100_fcw_ld *fcw, > > + union acc100_harq_layout_data *harq_layout); > > + > > /* Private data structure for each ACC100 device */ struct > > acc100_device { > > void *mmio_base; /**< Base address of MMIO registers (BAR0) */ > @@ > > -605,6 +614,8 @@ struct acc100_device { > > uint16_t q_assigned_bit_map[ACC100_NUM_QGRPS]; > > bool pf_device; /**< True if this is a PF ACC100 device */ > > bool configured; /**< True if this ACC100 device is configured */ > > + uint16_t device_variant; /**< Device variant */ > > + acc10x_fcw_ld_fill_fun_t fcw_ld_fill; /**< 5GUL FCW generation > > function */ > > }; > > > > /** > > diff --git a/drivers/baseband/acc100/rte_acc101_pmd.h > > b/drivers/baseband/acc100/rte_acc101_pmd.h > > new file mode 100644 > > index 0000000..8f1f4ab > > --- /dev/null > > +++ b/drivers/baseband/acc100/rte_acc101_pmd.h >=20 > This file is internal, shouldn't we drop the rte? There is lack of consistency on the filenaming really historically, still w= ill update the new file. Thanks >=20 >=20 > > @@ -0,0 +1,55 @@ > > +/* SPDX-License-Identifier: BSD-3-Clause > > + * Copyright(c) 2022 Intel Corporation */ > > + > > +/* ACC101 PCI vendor & device IDs */ > > +#define RTE_ACC101_VENDOR_ID (0x8086) > > +#define RTE_ACC101_PF_DEVICE_ID (0x57c4) > > +#define RTE_ACC101_VF_DEVICE_ID (0x57c5) > > + > > +/* Define as 1 to use only a single FEC engine */ #ifndef > > +RTE_ACC101_SINGLE_FEC #define RTE_ACC101_SINGLE_FEC 0 #endif >=20 > Also the above defines should drop RTE if they are internal symbols. This is historical as well but will update on current code first with addit= ional commit. Thanks=20 >=20 > > + > > +/* Number of Virtual Functions ACC101 supports */ > > +#define ACC101_NUM_VFS 16 > > +#define ACC101_NUM_QGRPS 8 > > +#define ACC101_NUM_AQS 16 > > +/* All ACC101 Registers alignment are 32bits =3D 4B */ > > +#define ACC101_BYTES_IN_WORD 4 > > + > > +#define ACC101_TMPL_PRI_0 0x03020100 > > +#define ACC101_TMPL_PRI_1 0x07060504 > > +#define ACC101_TMPL_PRI_2 0x0b0a0908 > > +#define ACC101_TMPL_PRI_3 0x0f0e0d0c > > +#define ACC101_WORDS_IN_ARAM_SIZE (128 * 1024 / 4) > > + > > +#define ACC101_NUM_TMPL 32 > > +/* Mapping of signals for the available engines */ > > +#define ACC101_SIG_UL_5G 0 > > +#define ACC101_SIG_UL_5G_LAST 8 > > +#define ACC101_SIG_DL_5G 13 > > +#define ACC101_SIG_DL_5G_LAST 15 > > +#define ACC101_SIG_UL_4G 16 > > +#define ACC101_SIG_UL_4G_LAST 19 > > +#define ACC101_SIG_DL_4G 27 > > +#define ACC101_SIG_DL_4G_LAST 31 > > +#define ACC101_NUM_ACCS 5 > > +#define ACC101_PF_VAL 2 > > + > > +/* ACC101 Configuration */ > > +#define ACC101_CFG_DMA_ERROR 0x3D7 > > +#define ACC101_CFG_AXI_CACHE 0x11 > > +#define ACC101_CFG_QMGR_HI_P 0x0F0F > > +#define ACC101_CFG_PCI_AXI 0xC003 > > +#define ACC101_CFG_PCI_BRIDGE 0x40006033 > > +#define ACC101_ENGINE_OFFSET 0x1000 > > +#define ACC101_LONG_WAIT 1000 > > +#define ACC101_GPEX_AXIMAP_NUM 17 > > +#define ACC101_CLOCK_GATING_EN 0x30000 > > +#define ACC101_DMA_INBOUND 0x104 > > +/* DDR Size per VF - 512MB by default > > + * Can be increased up to 4 GB with single PF/VF */ > > +#define ACC101_HARQ_DDR (512 * 1) > > -- > > 1.8.3.1