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Miller" , Jason Gunthorpe , Leon Romanovsky , "netdev@vger.kernel.org" , "linux-rdma@vger.kernel.org" , David Ahern , Jacob Keller , Sridhar Samudrala , "david.m.ertman@intel.com" , "dan.j.williams@intel.com" , "kiran.patil@intel.com" , "gregkh@linuxfoundation.org" , Jiri Pirko , Vu Pham , Saeed Mahameed Subject: RE: [net-next v5 03/15] devlink: Introduce PCI SF port flavour and port attribute Thread-Topic: [net-next v5 03/15] devlink: Introduce PCI SF port flavour and port attribute Thread-Index: AQHW0sFHdQ+yzn0pRUyP/4UDzcNU4Kn4zj8AgABFQ1A= Date: Wed, 16 Dec 2020 03:42:51 +0000 Message-ID: References: <20201215090358.240365-1-saeed@kernel.org> <20201215090358.240365-4-saeed@kernel.org> <20201215152740.0b3ed376@kicinski-fedora-pc1c0hjn.dhcp.thefacebook.com> In-Reply-To: <20201215152740.0b3ed376@kicinski-fedora-pc1c0hjn.dhcp.thefacebook.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: kernel.org; dkim=none (message not signed) header.d=none;kernel.org; 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b=QKTBGdy/cJxCQz9jLseSh+fR6nJIUUVh7eE0QxaAXeTZMG4ykqSSHui+A0A/i0+k3 HrRzEfzFy1T8jxAR0k9e+5HoONC5gfmLBydOqef/JkAdQmONT0jRFNRjO+1b0OrjHf PxGkwIdJY8L3Jw7Rr52sweADJbkrqHHpRaMh9+Bkd4Om1rg3X3bN21VBZ0HPrjzSAr f4uQDezZH9jb3hiaKE9nokJg7MwyexT5HEDAG/vUG0eBZ9nswvR5Qk+PvV0pCb6mTc +ERBWEulHKCL4SKTOTAjP4mVZ4GQUGKX4712gbHjpHgb2mXQin7I9kHlIoSkCiTRiO GR/HImcYtbGcg== Precedence: bulk List-ID: X-Mailing-List: linux-rdma@vger.kernel.org > From: Jakub Kicinski > Sent: Wednesday, December 16, 2020 4:58 AM >=20 > On Tue, 15 Dec 2020 01:03:46 -0800 Saeed Mahameed wrote: > > + * devlink_port_attrs_pci_sf_set - Set PCI SF port attributes > > + * > > + * @devlink_port: devlink port > > + * @controller: associated controller number for the devlink port > instance > > + * @pf: associated PF for the devlink port instance > > + * @sf: associated SF of a PF for the devlink port instance > > + * @external: indicates if the port is for an external controller > > + */ > > +void devlink_port_attrs_pci_sf_set(struct devlink_port *devlink_port, = u32 > controller, > > + u16 pf, u32 sf, bool external) { > > + struct devlink_port_attrs *attrs =3D &devlink_port->attrs; > > + int ret; > > + > > + if (WARN_ON(devlink_port->registered)) > > + return; > > + ret =3D __devlink_port_attrs_set(devlink_port, > DEVLINK_PORT_FLAVOUR_PCI_SF); > > + if (ret) > > + return; > > + attrs->pci_sf.controller =3D controller; > > + attrs->pci_sf.pf =3D pf; > > + attrs->pci_sf.sf =3D sf; > > + attrs->pci_sf.external =3D external; > > +} > > +EXPORT_SYMBOL_GPL(devlink_port_attrs_pci_sf_set); >=20 > So subfunctions don't have a VF id but they may have a controller? > Right. SF can be on external controller. =20 > Can you tell us more about the use cases and deployment models you're > intending to support? Let's not add attributes and info which will go unu= sed. >=20 External will be used the same way how it is used for PF and VF. > How are SFs supposed to be used with SmartNICs? Are you assuming single > domain of control? No. it is not assumed. SF can be deployed from smartnic to external host. A user has to pass appropriate controller number, pf number attributes duri= ng creation time. > It seems that the way the industry is moving the major > use case for SmartNICs is bare metal. >=20 > I always assumed nested eswitches when thinking about SmartNICs, what > are you intending to do? > Mlx5 doesn't support nested eswitch. SF can be deployed on the external con= troller PCI function. But this interface neither limited nor enforcing nested or flat eswitch. =20 > What are your plans for enabling this feature in user space project? Do you mean K8s plugin or iproute2? Can you please tell us what user space = project? If iproute2, will send the iproute2 patchset like other patchset pointing t= o kernel uapi headers..