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Thu, 11 Jul 2019 04:14:45 +0000 From: Tyler Baicar OS To: James Morse , "mark.rutland@arm.com" CC: "lorenzo.pieralisi@arm.com" , "catalin.marinas@arm.com" , "sudeep.holla@arm.com" , "rjw@rjwysocki.net" , "linux-kernel@vger.kernel.org" , "Matteo.Carlini@arm.com" , "linux-acpi@vger.kernel.org" , "tony.luck@intel.com" , "bp@alien8.de" , "guohanjun@huawei.com" , "Andrew.Murray@arm.com" , Open Source Submission , "lenb@kernel.org" , "will@kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-edac@vger.kernel.org" Subject: Re: [PATCH RFC 2/4] arm64: mm: Add RAS extension system register check to SEA handling Thread-Topic: [PATCH RFC 2/4] arm64: mm: Add RAS extension system register check to SEA handling Thread-Index: AQHVMPZvV84yhcAYOk+DNBn1Cdw2C6bAhfiAgAKLP66AAcNd4A== Date: Thu, 11 Jul 2019 04:14:45 +0000 Message-ID: References: <1562086280-5351-1-git-send-email-baicar@os.amperecomputing.com> <1562086280-5351-3-git-send-email-baicar@os.amperecomputing.com>, , In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=baicar@os.amperecomputing.com; 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received-spf: None (protection.outlook.com: os.amperecomputing.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: KL+oScjiwncfzVQjXVLRwBmFA8lKFJN7qbVGMlqt9K4QQuxb/n/yk9G4c5QWHTkDybDyofbBi7lEZyBcB7yG4J9V3Zl0dz7iKamvW7W51V/ITvu6as6A9q3KRJS/awKJ+Bf5xt/4Zhmi90sobkrFWy0sKipydAaZ6twD9ZtdyM58G89tM8MEl0icH2xSa+h6nyY9VVMnCG8INIbd+J1vT+WtaRknlCGPUIFQC3ChEXpTq8yawy0dw4fS2MXOSOqEiACluoUAL8k/Fx4ClD0c/LLmiENDhKXDF2VNIpIdVhJbdmHDE6HtRgC7FmzsQZFdo2d3lbFDl6ekjXA2kFur5kaL299ZLk6aOlepBDDL5JG7rEkprKCz93o+xsqXiGJ0SzMxqFWx3QAsCaeCIhMI+6dopov0wUm3ki/H2jmmczw= Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: os.amperecomputing.com X-MS-Exchange-CrossTenant-Network-Message-Id: 26b1db25-433e-4007-7f84-08d705b64e9a X-MS-Exchange-CrossTenant-originalarrivaltime: 11 Jul 2019 04:14:45.5520 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3bc2b170-fd94-476d-b0ce-4229bdc904a7 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Baicar@os.amperecomputing.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR01MB4055 Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org Hi James, Mark, On Tue, Jul 9, 2019 at 8:52 PM Tyler Baicar OS wrote: > On Mon, Jul 8, 2019 at 10:10 AM James Morse wrote: > > On 02/07/2019 17:51, Tyler Baicar OS wrote: > > > @@ -632,6 +633,8 @@ static int do_sea(unsigned long addr, unsigned in= t esr, struct pt_regs *regs) > > > > > > inf =3D esr_to_fault_info(esr); > > > > > > + arch_arm_ras_report_error(); > > > + > > > /* > > > * Return value ignored as we rely on signal merging. > > > * Future patches will make this more robust. > > > > > > > If we interrupted a preemptible context, do_sea() is preemptible too...= This means we > > can't know if we're still running on the same CPU as the one that took = the external-abort. > > (until this series, it hasn't mattered). > > > > Fixing this means cramming something into entry.S's el1_da, as this may= unmask interrupts > > before calling do_mem_abort(). But its going to be ugly because some of= do_mem_abort()s > > ESR values need to be preemptible because they sleep, e.g. page-faults = calling > > handle_mm_fault(). > > For do_sea(), do_exit() will 'fix' the preempt count if we kill the thr= ead, but if we > > don't, it still needs to be balanced. Doing all this in assembly is goi= ng to be unreadable! > > > > Mark Rutland has a series to move the entry assembly into C [0]. Based = on that that it > > should be possible for the new el1_abort() to spot a Synchronous-Extern= al-Abort ESR, and > > wrap the do_mem_abort() with preempt enable/disable, before inheriting = the flags. (which > > for synchronous exceptions, I think we should always do) > > > > [0] https://git.kernel.org/pub/scm/linux/kernel/git/mark/linux.git/log/= ?h=3Darm64/entry-deasm > > Hey James, > > Good catch! I didn't think the synchronous route was preemptible. > > I wasn't seeing this issue when testing this on emulation, but I was able= to > test and prove the issue on a Neoverse N1 SDP: > > root@genericarmv8:~# echo 0x100000000 > /proc/cached_read > [ 42.985622] Reading from address 0x100000000 > [ 42.989893] WARNING: CPU: 0 PID: 2812 at /home/tyler/neoverse/arm-refe= rence- > platforms/linux/arch/arm64/kernel/cpufeature.c:1940 this_cpu_has_cap+0x68= /0x78 > [..] > [ 43.119083] Call trace: > [ 43.121515] this_cpu_has_cap+0x68/0x78 > [ 43.125338] do_sea+0x34/0x70 > [ 43.128292] do_mem_abort+0x3c/0x98 > [ 43.131765] el1_da+0x20/0x94 > [ 43.134722] cached_read+0x30/0x68 > [ 43.138112] simple_attr_write+0xbc/0x128 > [ 43.142109] proc_reg_write+0x60/0xa8 > [ 43.145757] __vfs_write+0x18/0x40 > [ 43.149145] vfs_write+0xa4/0x1b8 > [ 43.152445] ksys_write+0x64/0xe0 > [ 43.155746] __arm64_sys_write+0x14/0x20 > [ 43.159654] el0_svc_common.constprop.0+0xa8/0x100 > [ 43.164430] el0_svc_handler+0x28/0x78 > [ 43.168165] el0_svc+0x8/0xc > [ 43.171031] ---[ end trace 2c27619659261a1d ]--- > [ 43.175647] Internal error: synchronous external abort: 96000410 [#1] > PREEMPT SMP > [..] > > That warning is because it's preemptible: > > if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { > > I'll pull Mark's series in and add the preempt enable/disable around the = call > to do_mem_abort() in el1_abort() and test that out! I was able to pull in the series mentioned [0] and add a patch to wrap do_mem_abort with preempt disable/enable and the warning has gone away. diff --git a/arch/arm64/kernel/entry-common.c b/arch/arm64/kernel/entry-com= mon.c index 43aa78331e72..26cdf7db511a 100644 --- a/arch/arm64/kernel/entry-common.c +++ b/arch/arm64/kernel/entry-common.c @@ -118,7 +118,25 @@ static void el1_abort(struct pt_regs *regs, unsigned l= ong esr) unsigned long far =3D read_sysreg(far_el1); local_daif_inherit(regs); far =3D untagged_addr(far); - do_mem_abort(far, esr, regs); + + switch (esr & ESR_ELx_FSC) { + case ESR_ELx_FSC_EXTABT: // Synchronous External Abort + case 0x14: // SEA level 0 translation table walk + case 0x15: // SEA level 1 translation table walk + case 0x16: // SEA level 2 translation table walk + case 0x17: // SEA level 3 translation table walk + case 0x18: // Synchronous ECC error + case 0x1c: // SECC level 0 translation table walk + case 0x1d: // SECC level 1 translation table walk + case 0x1e: // SECC level 2 translation table walk + case 0x1f: // SECC level 3 translation table walk + preempt_disable(); + do_mem_abort(far, esr, regs); + preempt_enable(); + break; + default: + do_mem_abort(far, esr, regs); + }; } =20 /* Stack or PC alignment exception handling */ --=20 Is that what you had in mind James? Has this series [0] been accepted and is just waiting to be pulled now? Do you want me to add tested-by? Thanks, Tyler [0] https://git.kernel.org/pub/scm/linux/kernel/git/mark/linux.git/log/?h= =3Darm64/entry-deasm= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D349CC74A42 for ; Thu, 11 Jul 2019 04:15:12 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A60B2206B8 for ; Thu, 11 Jul 2019 04:15:12 +0000 (UTC) Authentication-Results: mail.kernel.org; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi James, Mark, On Tue, Jul 9, 2019 at 8:52 PM Tyler Baicar OS wrote: > On Mon, Jul 8, 2019 at 10:10 AM James Morse wrote: > > On 02/07/2019 17:51, Tyler Baicar OS wrote: > > > @@ -632,6 +633,8 @@ static int do_sea(unsigned long addr, unsigned int esr, struct pt_regs *regs) > > > > > > inf = esr_to_fault_info(esr); > > > > > > + arch_arm_ras_report_error(); > > > + > > > /* > > > * Return value ignored as we rely on signal merging. > > > * Future patches will make this more robust. > > > > > > > If we interrupted a preemptible context, do_sea() is preemptible too... This means we > > can't know if we're still running on the same CPU as the one that took the external-abort. > > (until this series, it hasn't mattered). > > > > Fixing this means cramming something into entry.S's el1_da, as this may unmask interrupts > > before calling do_mem_abort(). But its going to be ugly because some of do_mem_abort()s > > ESR values need to be preemptible because they sleep, e.g. page-faults calling > > handle_mm_fault(). > > For do_sea(), do_exit() will 'fix' the preempt count if we kill the thread, but if we > > don't, it still needs to be balanced. Doing all this in assembly is going to be unreadable! > > > > Mark Rutland has a series to move the entry assembly into C [0]. Based on that that it > > should be possible for the new el1_abort() to spot a Synchronous-External-Abort ESR, and > > wrap the do_mem_abort() with preempt enable/disable, before inheriting the flags. (which > > for synchronous exceptions, I think we should always do) > > > > [0] https://git.kernel.org/pub/scm/linux/kernel/git/mark/linux.git/log/?h=arm64/entry-deasm > > Hey James, > > Good catch! I didn't think the synchronous route was preemptible. > > I wasn't seeing this issue when testing this on emulation, but I was able to > test and prove the issue on a Neoverse N1 SDP: > > root@genericarmv8:~# echo 0x100000000 > /proc/cached_read > [ 42.985622] Reading from address 0x100000000 > [ 42.989893] WARNING: CPU: 0 PID: 2812 at /home/tyler/neoverse/arm-reference- > platforms/linux/arch/arm64/kernel/cpufeature.c:1940 this_cpu_has_cap+0x68/0x78 > [..] > [ 43.119083] Call trace: > [ 43.121515] this_cpu_has_cap+0x68/0x78 > [ 43.125338] do_sea+0x34/0x70 > [ 43.128292] do_mem_abort+0x3c/0x98 > [ 43.131765] el1_da+0x20/0x94 > [ 43.134722] cached_read+0x30/0x68 > [ 43.138112] simple_attr_write+0xbc/0x128 > [ 43.142109] proc_reg_write+0x60/0xa8 > [ 43.145757] __vfs_write+0x18/0x40 > [ 43.149145] vfs_write+0xa4/0x1b8 > [ 43.152445] ksys_write+0x64/0xe0 > [ 43.155746] __arm64_sys_write+0x14/0x20 > [ 43.159654] el0_svc_common.constprop.0+0xa8/0x100 > [ 43.164430] el0_svc_handler+0x28/0x78 > [ 43.168165] el0_svc+0x8/0xc > [ 43.171031] ---[ end trace 2c27619659261a1d ]--- > [ 43.175647] Internal error: synchronous external abort: 96000410 [#1] > PREEMPT SMP > [..] > > That warning is because it's preemptible: > > if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { > > I'll pull Mark's series in and add the preempt enable/disable around the call > to do_mem_abort() in el1_abort() and test that out! I was able to pull in the series mentioned [0] and add a patch to wrap do_mem_abort with preempt disable/enable and the warning has gone away. diff --git a/arch/arm64/kernel/entry-common.c b/arch/arm64/kernel/entry-common.c index 43aa78331e72..26cdf7db511a 100644 --- a/arch/arm64/kernel/entry-common.c +++ b/arch/arm64/kernel/entry-common.c @@ -118,7 +118,25 @@ static void el1_abort(struct pt_regs *regs, unsigned long esr) unsigned long far = read_sysreg(far_el1); local_daif_inherit(regs); far = untagged_addr(far); - do_mem_abort(far, esr, regs); + + switch (esr & ESR_ELx_FSC) { + case ESR_ELx_FSC_EXTABT: // Synchronous External Abort + case 0x14: // SEA level 0 translation table walk + case 0x15: // SEA level 1 translation table walk + case 0x16: // SEA level 2 translation table walk + case 0x17: // SEA level 3 translation table walk + case 0x18: // Synchronous ECC error + case 0x1c: // SECC level 0 translation table walk + case 0x1d: // SECC level 1 translation table walk + case 0x1e: // SECC level 2 translation table walk + case 0x1f: // SECC level 3 translation table walk + preempt_disable(); + do_mem_abort(far, esr, regs); + preempt_enable(); + break; + default: + do_mem_abort(far, esr, regs); + }; } /* Stack or PC alignment exception handling */ -- Is that what you had in mind James? Has this series [0] been accepted and is just waiting to be pulled now? Do you want me to add tested-by? Thanks, Tyler [0] https://git.kernel.org/pub/scm/linux/kernel/git/mark/linux.git/log/?h=arm64/entry-deasm _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel