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From: Taylor Simpson <tsimpson@quicinc.com>
To: Alessandro Di Federico <ale.qemu@rev.ng>,
	"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Cc: Alessandro Di Federico <ale@rev.ng>,
	Brian Cain <bcain@quicinc.com>,
	"richard.henderson@linaro.org" <richard.henderson@linaro.org>,
	"babush@rev.ng" <babush@rev.ng>, "nizzo@rev.ng" <nizzo@rev.ng>,
	"philmd@redhat.com" <philmd@redhat.com>
Subject: RE: [PATCH v5 06/14] target/hexagon: introduce new helper functions
Date: Wed, 23 Jun 2021 18:49:00 +0000	[thread overview]
Message-ID: <BYAPR02MB488670553BE40D6C7E385E31DE089@BYAPR02MB4886.namprd02.prod.outlook.com> (raw)
In-Reply-To: <20210619093713.1845446-7-ale.qemu@rev.ng>



> -----Original Message-----
> From: Alessandro Di Federico <ale.qemu@rev.ng>
> Sent: Saturday, June 19, 2021 3:37 AM
> To: qemu-devel@nongnu.org
> Cc: Taylor Simpson <tsimpson@quicinc.com>; Brian Cain
> <bcain@quicinc.com>; babush@rev.ng; nizzo@rev.ng; philmd@redhat.com;
> richard.henderson@linaro.org; Alessandro Di Federico <ale@rev.ng>
> Subject: [PATCH v5 06/14] target/hexagon: introduce new helper functions
> 
> From: Niccolò Izzo <nizzo@rev.ng>
> 
> These helpers will be employed by the idef-parser generated code.
> 
> Signed-off-by: Alessandro Di Federico <ale@rev.ng>
> Signed-off-by: Niccolò Izzo <nizzo@rev.ng>
> ---
>  target/hexagon/genptr.c | 163
> ++++++++++++++++++++++++++++++++++++----
>  target/hexagon/genptr.h |  23 ++++++
>  target/hexagon/macros.h |   9 +++
>  3 files changed, 180 insertions(+), 15 deletions(-)
> 
> diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index
> 6f2816f6e2..cf45c28f58 100644
> --- a/target/hexagon/genptr.c
> +++ b/target/hexagon/genptr.c
> @@ -28,6 +28,12 @@
>  #include "gen_tcg.h"
>  #include "genptr.h"
> 
> +TCGv gen_read_reg(TCGv result, int num) {
> +    tcg_gen_mov_tl(result, hex_gpr[num]);
> +    return result;
> +}
> +
>  TCGv gen_read_preg(TCGv pred, uint8_t num)  {
>      tcg_gen_mov_tl(pred, hex_pred[num]); @@ -396,18 +402,19 @@ static
> inline void gen_store_conditional8(CPUHexagonState *env,
>      tcg_gen_movi_tl(hex_llsc_addr, ~0);  }
> 
> -static inline void gen_store32(TCGv vaddr, TCGv src, int width, int slot)
> +void gen_store32(DisasContext *ctx, TCGv vaddr, TCGv src, tcg_target_long
> width,
> +                 unsigned slot)

uint32_t

>  {
>      tcg_gen_mov_tl(hex_store_addr[slot], vaddr);
>      tcg_gen_movi_tl(hex_store_width[slot], width);
>      tcg_gen_mov_tl(hex_store_val32[slot], src);
> +    ctx->store_width[slot] = width;
>  }
> 
> -static inline void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src,
> -                              DisasContext *ctx, int slot)
> +void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext
> *ctx,
> +                unsigned slot)
>  {
> -    gen_store32(vaddr, src, 1, slot);
> -    ctx->store_width[slot] = 1;
> +    gen_store32(ctx, vaddr, src, 1, slot);
>  }
> 
>  static inline void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src,
> @@ -418,11 +425,10 @@ static inline void gen_store1i(TCGv_env cpu_env,
> TCGv vaddr, int32_t src,
>      tcg_temp_free(tmp);
>  }
> 
> -static inline void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src,
> -                              DisasContext *ctx, int slot)
> +void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext
> *ctx,
> +                unsigned slot)
>  {
> -    gen_store32(vaddr, src, 2, slot);
> -    ctx->store_width[slot] = 2;
> +    gen_store32(ctx, vaddr, src, 2, slot);
>  }
> 
>  static inline void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src,
> @@ -433,11 +439,10 @@ static inline void gen_store2i(TCGv_env cpu_env,
> TCGv vaddr, int32_t src,
>      tcg_temp_free(tmp);
>  }
> 
> -static inline void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src,
> -                              DisasContext *ctx, int slot)
> +void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext
> *ctx,
> +                unsigned slot)
>  {
> -    gen_store32(vaddr, src, 4, slot);
> -    ctx->store_width[slot] = 4;
> +    gen_store32(ctx, vaddr, src, 4, slot);
>  }
> 
>  static inline void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src,
> @@ -448,8 +453,8 @@ static inline void gen_store4i(TCGv_env cpu_env,
> TCGv vaddr, int32_t src,
>      tcg_temp_free(tmp);
>  }
> 
> -static inline void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src,
> -                              DisasContext *ctx, int slot)
> +void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src,
> DisasContext *ctx,
> +                unsigned slot)
>  {
>      tcg_gen_mov_tl(hex_store_addr[slot], vaddr);
>      tcg_gen_movi_tl(hex_store_width[slot], 8); @@ -476,5 +481,133 @@
> static TCGv gen_8bitsof(TCGv result, TCGv value)
>      return result;
>  }
> 
> +void gen_set_usr_field(int field, TCGv val) {
> +    tcg_gen_deposit_tl(hex_gpr[HEX_REG_USR], hex_gpr[HEX_REG_USR],
> val,
> +                       reg_field_info[field].offset,
> +                       reg_field_info[field].width); }
> +
> +void gen_set_usr_fieldi(int field, int x) {
> +    TCGv val = tcg_const_tl(x);
> +    gen_set_usr_field(field, val);
> +    tcg_temp_free(val);
> +}
> +
> +void gen_write_new_pc(TCGv addr)
> +{
> +    /* If there are multiple branches in a packet, ignore the second one */
> +    TCGv zero = tcg_const_tl(0);
> +    tcg_gen_movcond_tl(TCG_COND_NE, hex_next_PC, hex_branch_taken,
> zero,
> +                       hex_next_PC, addr);
> +    tcg_gen_movi_tl(hex_branch_taken, 1);
> +    tcg_temp_free(zero);
> +}
> +
> +void gen_sat_i32(TCGv dest, TCGv source, int width) {
> +    TCGv max_val = tcg_const_i32((1 << (width - 1)) - 1);
> +    TCGv min_val = tcg_const_i32(-(1 << (width - 1)));

Use _tl suffix, not _i32.

> +    tcg_gen_smin_tl(dest, source, max_val);
> +    tcg_gen_smax_tl(dest, dest, min_val);
> +    tcg_temp_free_i32(max_val);
> +    tcg_temp_free_i32(min_val);

Ditto

> +}
> +
> +void gen_sat_i32_ext(TCGv ovfl, TCGv dest, TCGv source, int width) {

gen_set_i32_ovfl would be a better name - ditto for the other _ext flavors later in this file

> +    gen_sat_i32(dest, source, width);
> +    tcg_gen_setcond_i32(TCG_COND_NE, ovfl, source, dest); }
> +
> +void gen_satu_i32(TCGv dest, TCGv source, int width) {
> +    TCGv max_val = tcg_const_i32((1 << width) - 1);
> +    tcg_gen_movcond_i32(TCG_COND_GTU, dest, source, max_val,
> max_val, source);
> +    TCGv_i32 zero = tcg_const_i32(0);
> +    tcg_gen_movcond_i32(TCG_COND_LT, dest, source, zero, zero, dest);
> +    tcg_temp_free_i32(max_val);
> +    tcg_temp_free_i32(zero);

_tl instead of _i32 for all of the above

For Hexagon, use _tl for all 32 bit operations.

> +}
> +
> +void gen_satu_i32_ext(TCGv ovfl, TCGv dest, TCGv source, int width) {
> +    gen_satu_i32(dest, source, width);
> +    tcg_gen_setcond_i32(TCG_COND_NE, ovfl, source, dest); }
> +
> +void gen_sat_i64(TCGv_i64 dest, TCGv_i64 source, int width) {
> +    TCGv_i64 max_val = tcg_const_i64((1 << (width - 1)) - 1);
> +    TCGv_i64 min_val = tcg_const_i64(-(1 << (width - 1)));
> +    tcg_gen_smin_i64(dest, source, max_val);
> +    tcg_gen_smax_i64(dest, dest, min_val);
> +    tcg_temp_free_i64(max_val);
> +    tcg_temp_free_i64(min_val);
> +}
> +
> +void gen_sat_i64_ext(TCGv ovfl, TCGv_i64 dest, TCGv_i64 source, int
> +width) {
> +    gen_sat_i64(dest, source, width);
> +    TCGv_i64 ovfl_64 = tcg_temp_new_i64();
> +    tcg_gen_setcond_i64(TCG_COND_NE, ovfl_64, dest, source);
> +    tcg_gen_trunc_i64_tl(ovfl, ovfl_64);
> +    tcg_temp_free_i64(ovfl_64);
> +}
> +
> +void gen_satu_i64(TCGv_i64 dest, TCGv_i64 source, int width) {
> +    TCGv_i64 max_val = tcg_const_i64((1 << width) - 1);
> +    tcg_gen_movcond_i64(TCG_COND_GTU, dest, source, max_val,
> max_val, source);
> +    TCGv_i64 zero = tcg_const_i64(0);
> +    tcg_gen_movcond_i64(TCG_COND_LT, dest, source, zero, zero, dest);
> +    tcg_temp_free_i64(max_val);
> +    tcg_temp_free_i64(zero);
> +}
> +
> +void gen_satu_i64_ext(TCGv ovfl, TCGv_i64 dest, TCGv_i64 source, int
> +width) {
> +    gen_sat_i64(dest, source, width);
> +    TCGv_i64 ovfl_64 = tcg_temp_new_i64();
> +    tcg_gen_setcond_i64(TCG_COND_NE, ovfl_64, dest, source);
> +    tcg_gen_trunc_i64_tl(ovfl, ovfl_64);
> +    tcg_temp_free_i64(ovfl_64);
> +}
> +
> +void gen_fbrev(TCGv result, TCGv src)
> +{
> +    TCGv lo = tcg_temp_new();
> +    TCGv tmp1 = tcg_temp_new();
> +    TCGv tmp2 = tcg_temp_new();
> +
> +    /* Bit reversal of low 16 bits */
> +    tcg_gen_extract_tl(lo, src, 0, 16);
> +    tcg_gen_andi_tl(tmp1, lo, 0xaaaa);
> +    tcg_gen_shri_tl(tmp1, tmp1, 1);
> +    tcg_gen_andi_tl(tmp2, lo, 0x5555);
> +    tcg_gen_shli_tl(tmp2, tmp2, 1);
> +    tcg_gen_or_tl(lo, tmp1, tmp2);
> +    tcg_gen_andi_tl(tmp1, lo, 0xcccc);
> +    tcg_gen_shri_tl(tmp1, tmp1, 2);
> +    tcg_gen_andi_tl(tmp2, lo, 0x3333);
> +    tcg_gen_shli_tl(tmp2, tmp2, 2);
> +    tcg_gen_or_tl(lo, tmp1, tmp2);
> +    tcg_gen_andi_tl(tmp1, lo, 0xf0f0);
> +    tcg_gen_shri_tl(tmp1, tmp1, 4);
> +    tcg_gen_andi_tl(tmp2, lo, 0x0f0f);
> +    tcg_gen_shli_tl(tmp2, tmp2, 4);
> +    tcg_gen_or_tl(lo, tmp1, tmp2);
> +    tcg_gen_bswap16_tl(lo, lo);
> +
> +    /* Final tweaks */
> +    tcg_gen_deposit_tl(result, src, lo, 0, 16);
> +    tcg_gen_or_tl(result, result, lo);
> +
> +    tcg_temp_free(lo);
> +    tcg_temp_free(tmp1);
> +    tcg_temp_free(tmp2);
> +}
> +

Use gen_helper_fbrev instead of this one.

>  #include "tcg_funcs_generated.c.inc"
>  #include "tcg_func_table_generated.c.inc"
> diff --git a/target/hexagon/genptr.h b/target/hexagon/genptr.h index
> 709b8eb099..48d1a32f49 100644
> --- a/target/hexagon/genptr.h
> +++ b/target/hexagon/genptr.h
> @@ -24,8 +24,31 @@
> 
>  extern const SemanticInsn opcode_genptr[];
> 
> +TCGv gen_read_reg(TCGv result, int num);
>  TCGv gen_read_preg(TCGv pred, uint8_t num);  void gen_log_reg_write(int
> rnum, TCGv val);  void gen_log_pred_write(DisasContext *ctx, int pnum,
> TCGv val);
> +void gen_store32(DisasContext *ctx, TCGv vaddr, TCGv src, tcg_target_long
> width,
> +                 unsigned slot);
> +void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext
> *ctx,
> +                unsigned slot);
> +void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext
> *ctx,
> +                unsigned slot);
> +void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext
> *ctx,
> +                unsigned slot);
> +void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src,
> DisasContext *ctx,
> +                unsigned slot);
> +void gen_write_new_pc(TCGv addr);
> +void gen_set_usr_field(int field, TCGv val); void
> +gen_set_usr_fieldi(int field, int x); void gen_sat_i32(TCGv dest, TCGv
> +source, int width); void gen_sat_i32_ext(TCGv ovfl, TCGv dest, TCGv
> +source, int width); void gen_satu_i32(TCGv dest, TCGv source, int
> +width); void gen_satu_i32_ext(TCGv ovfl, TCGv dest, TCGv source, int
> +width); void gen_sat_i64(TCGv_i64 dest, TCGv_i64 source, int width);
> +void gen_sat_i64_ext(TCGv ovfl, TCGv_i64 dest, TCGv_i64 source, int
> +width); void gen_satu_i64(TCGv_i64 dest, TCGv_i64 source, int width);
> +void gen_satu_i64_ext(TCGv ovfl, TCGv_i64 dest, TCGv_i64 source, int
> +width); void gen_fbrev(TCGv result, TCGv src);
> 
>  #endif
> diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h index
> eadb7e5d05..7d09501844 100644
> --- a/target/hexagon/macros.h
> +++ b/target/hexagon/macros.h
> @@ -181,7 +181,16 @@
>  #define MEM_STORE8(VA, DATA, SLOT) log_store64(env, VA, DATA, 8,
> SLOT)  #endif
> 
> +#ifdef QEMU_GENERATE
> +static inline void gen_cancel(unsigned slot) {

uint32_t

> +    tcg_gen_ori_tl(hex_slot_cancelled, hex_slot_cancelled, 1 << slot);
> +}
> +
> +#define CANCEL gen_cancel(slot);
> +#else
>  #define CANCEL cancel_slot(env, slot)
> +#endif
> 
>  #define LOAD_CANCEL(EA) do { CANCEL; } while (0)
> 
> --
> 2.31.1


  parent reply	other threads:[~2021-06-23 18:49 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-19  9:36 [PATCH v5 00/14] target/hexagon: introduce idef-parser Alessandro Di Federico via
2021-06-19  9:37 ` [PATCH v5 01/14] tcg: expose TCGCond manipulation routines Alessandro Di Federico via
2021-06-19 13:51   ` Richard Henderson
2021-06-19  9:37 ` [PATCH v5 02/14] target/hexagon: update MAINTAINERS for idef-parser Alessandro Di Federico via
2021-06-19  9:37 ` [PATCH v5 03/14] target/hexagon: import README " Alessandro Di Federico via
2021-06-23 15:46   ` Taylor Simpson
2021-06-24 13:51     ` Alessandro Di Federico via
2021-06-19  9:37 ` [PATCH v5 04/14] target/hexagon: make slot number an unsigned Alessandro Di Federico via
2021-06-23 15:58   ` Taylor Simpson
2021-06-19  9:37 ` [PATCH v5 05/14] target/hexagon: make helper functions non-static Alessandro Di Federico via
2021-06-23 18:29   ` Taylor Simpson
2021-06-19  9:37 ` [PATCH v5 06/14] target/hexagon: introduce new helper functions Alessandro Di Federico via
2021-06-23 12:05   ` Taylor Simpson
2021-06-23 18:49   ` Taylor Simpson [this message]
2021-06-19  9:37 ` [PATCH v5 07/14] target/hexagon: expose next PC in DisasContext Alessandro Di Federico via
2021-06-23 18:54   ` Taylor Simpson
2021-06-19  9:37 ` [PATCH v5 08/14] target/hexagon: prepare input for the idef-parser Alessandro Di Federico via
2021-06-23 19:37   ` Taylor Simpson
2021-06-19  9:37 ` [PATCH v5 09/14] target/hexagon: import lexer for idef-parser Alessandro Di Federico via
2021-06-23 20:05   ` Taylor Simpson
2021-06-19  9:37 ` [PATCH v5 10/14] target/hexagon: import parser " Alessandro Di Federico via
2021-06-22 22:35   ` Taylor Simpson
2021-06-24  3:55   ` Taylor Simpson
2021-06-29 14:26     ` Alessandro Di Federico via
2021-06-30 16:51     ` Paolo Montesel
2021-07-05 16:47     ` Alessandro Di Federico via
2021-06-19  9:37 ` [PATCH v5 11/14] target/hexagon: call idef-parser functions Alessandro Di Federico via
2021-06-25 22:00   ` Taylor Simpson
2021-06-19  9:37 ` [PATCH v5 12/14] target/hexagon: remove unused macros and functions Alessandro Di Federico via
2021-06-25 22:02   ` Taylor Simpson
2021-06-19  9:37 ` [PATCH v5 13/14] target/hexagon: import additional tests Alessandro Di Federico via
2021-06-25 23:56   ` Taylor Simpson
2021-06-28 22:39     ` Taylor Simpson
2021-07-05 16:50     ` Alessandro Di Federico via
2021-06-19  9:37 ` [PATCH v5 14/14] gitlab-ci: do not use qemu-project Docker registry Alessandro Di Federico via
2021-06-29 14:26   ` Alessandro Di Federico via
2021-06-29 14:37   ` Daniel P. Berrangé
2021-07-08 16:00     ` Alessandro Di Federico via

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