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Thu, 30 Apr 2020 07:11:32 +0000 From: Bharat Kumar Gogada To: Rob Herring CC: "linux-pci@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "lorenzo.pieralisi@arm.com" , "bhelgaas@google.com" , Ravikiran Gummaluri Subject: RE: [PATCH v6 1/2] PCI: xilinx-cpm: Add device tree binding for Versal CPM Root Port Thread-Topic: [PATCH v6 1/2] PCI: xilinx-cpm: Add device tree binding for Versal CPM Root Port Thread-Index: AQHWGjB+ikn3pdln6kq5oTCz9BkyqaiQey2AgADLnxA= Date: Thu, 30 Apr 2020 07:11:32 +0000 Message-ID: References: <1587729844-20798-1-git-send-email-bharat.kumar.gogada@xilinx.com> <1587729844-20798-2-git-send-email-bharat.kumar.gogada@xilinx.com> <20200429185541.atk5k4j7rgh7ipmr@bogus> In-Reply-To: <20200429185541.atk5k4j7rgh7ipmr@bogus> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-TNEF-Correlator: authentication-results: kernel.org; dkim=none (message not signed) header.d=none;kernel.org; dmarc=none action=none header.from=xilinx.com; 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x-ms-exchange-antispam-messagedata: JmieLXetybiyL3A3o03AKDQmrnKXYlybKgD7/+KQ7Y5al3SZttv0+bgQnzpFVAswPJ7hxpgdt/CHfenVRd/ExxJWUNBp+sd8s7xET/DT8d0V08agK14P1seNeYzUgZm6sqQmeKjzJgfXZa+XgquUs251h6d6Qyt/yVoBnlFzg589skSX0JTz9TNJkwf06RLWjw1RBOyQxeBTY9IUJEMIHvbHeAWIjjF8RBKW5nDDTbHZTlwmIL4AzY7g8Zj10k9TCmZaMb9cBMZRbFqn+KzrXUajh+1NGtBo232ZsY0CaEwaYffVpgDczJ9oLXkEMkTGpzw6Jadb6oPKZG0RTqPaVdIDXET0cCqbQz4toioHpn7RCGHuVumtwOq2+Nw2GCsjWCUpZx2FPMWJMIJCeNOAKf747kXtr5cb6ExwF14w4IkaQqKFUT5xB2wIqIJeYq8UthLL7JJphU0kUw7dwrDR+GBN58fzzLf03aYiVO9bZZ8Sr4RtY5oFhQ6H94d4nxIOb4hVAgxukl0H3RlHlgm1M2DanQaTmCeAudVHmIyyzfRtHjw7LzgoA1uTuTVadbk4kaFvOSHROETc1x8xx9RVcRyaTzK4gBJzvYXwC9kVMul/hzzOWE1GqPKMBIBhxSs2xpjbumIMUsQ6xL8XSYiSuZPRDJ4yEkhRfLq2Dp8vBXfIVbtWsUVSoDTfUbFHNoS7flfmTAnKzxym+j65GP37YwSHx+ZkppSREGcb3TwlxKNA7pqkCY+kBr5TpktzMVspz8vt6B3tWxJOijalJE5gOF1qWtqVUQyIJkShQFsxSpg= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7a2d49ff-908c-4e1a-4756-08d7ecd5b678 X-MS-Exchange-CrossTenant-originalarrivaltime: 30 Apr 2020 07:11:32.8610 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 5rfTcJoDxyL0Zv7w7NNHw/W4wWcSu2WG88yNC+yLFc62TtKvyPU1vT9Fuvb6yPqthE4GcGTdif8JK4DIE07JNw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR02MB4631 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > On Fri, Apr 24, 2020 at 05:34:03PM +0530, Bharat Kumar Gogada wrote: > > Add device tree binding documentation for Versal CPM Root Port driver. > > > > Signed-off-by: Bharat Kumar Gogada > > --- > > .../devicetree/bindings/pci/xilinx-versal-cpm.txt | 68 > > ++++++++++++++++++++++ > > 1 file changed, 68 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/pci/xilinx-versal-cpm.txt >=20 > DT bindings need to Cc DT list to be reviewed. Bindings are now in DT sch= ema > format. See Documentation/devicetree/writing-schema.rst. >=20 > Sorry to tell you this on v6, but first I'm seeing it. Hi Rob, Thanks for the inputs, will fix this and send with schema format. Regards, Bharat >=20 > > > > diff --git > > a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.txt > > b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.txt > > new file mode 100644 > > index 0000000..eac6144 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.txt > > @@ -0,0 +1,68 @@ > > +* Xilinx Versal CPM DMA Root Port Bridge DT description > > + > > +Required properties: > > +- #address-cells: Address representation for root ports, set to <3> > > +- #size-cells: Size representation for root ports, set to <2> > > +- #interrupt-cells: specifies the number of cells needed to encode an > > + interrupt source. The value must be 1. > > +- compatible: Should contain "xlnx,versal-cpm-host-1.00" > > +- reg: Should contain configuration space (includes bridge registers) = and > > + CPM system level control and status registers, and length > > +- reg-names: Must include the following entries: > > + "cfg": configuration space region and bridge registers > > + "cpm_slcr": CPM system level control and status registers > > +- interrupts: Should contain AXI PCIe interrupt > > +- interrupt-map-mask, > > + interrupt-map: standard PCI properties to define the mapping of the > > + PCI interface to interrupt numbers. > > +- bus-range: Range of bus numbers associated with this controller > > +- ranges: ranges for the PCI memory regions (I/O space region is not > > + supported by hardware) > > + Please refer to the standard PCI bus binding document for a more > > + detailed explanation > > +- msi-map: Maps a Requester ID to an MSI controller and associated MSI > > + sideband data > > +- interrupt-names: Must include the following entries: > > + "misc": interrupt asserted when legacy or error interrupt is > > +received >=20 > Don't really need a name when only 1. >=20 > > + > > +Interrupt controller child node > > ++++++++++++++++++++++++++++++++ > > +Required properties: > > +- interrupt-controller: identifies the node as an interrupt > > +controller > > +- #address-cells: specifies the number of cells needed to encode an > > + address. The value must be 0. > > +- #interrupt-cells: specifies the number of cells needed to encode an > > + interrupt source. The value must be 1. > > + > > + > > +Refer to the following binding document for more detailed description > > +on the use of 'msi-map': > > + Documentation/devicetree/bindings/pci/pci-msi.txt > > + > > +Example: > > + pci@fca10000 { >=20 > Unit address is normally the first entry. >=20 > > + #address-cells =3D <3>; > > + #interrupt-cells =3D <1>; > > + #size-cells =3D <2>; > > + compatible =3D "xlnx,versal-cpm-host-1.00"; > > + interrupt-map =3D <0 0 0 1 &pcie_intc_0 0>, > > + <0 0 0 2 &pcie_intc_0 1>, > > + <0 0 0 3 &pcie_intc_0 2>, > > + <0 0 0 4 &pcie_intc_0 3>; > > + interrupt-map-mask =3D <0 0 0 7>; > > + interrupt-parent =3D <&gic>; > > + interrupt-names =3D "misc"; > > + interrupts =3D <0 72 4>; > > + bus-range =3D <0x00 0xff>; > > + ranges =3D <0x02000000 0x00000000 0xE0000000 0x0 > 0xE0000000 > > +0x00000000 0x10000000>, >=20 > lowercase hex please. >=20 > > + <0x43000000 0x00000080 0x00000000 0x00000080 > 0x00000000 0x00000000 0x80000000>; > > + msi-map =3D <0x0 &its_gic 0x0 0x10000>; > > + reg =3D <0x6 0x00000000 0x0 0x10000000>, > > + <0x0 0xFCA10000 0x0 0x1000>; > > + reg-names =3D "cfg", "cpm_slcr"; > > + pcie_intc_0: pci-interrupt-controller { >=20 > interrupt-controller { >=20 > > + #address-cells =3D <0>; > > + #interrupt-cells =3D <1>; > > + interrupt-controller ; > > + }; > > + }; > > -- > > 2.7.4 > >