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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 820c0ea8-e48f-4332-dc10-08d7b1c07dea X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Feb 2020 02:40:59.9266 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: ylLVHU7SUyaXUGmaO5C5M1+DpVFSjgVmE1jr510EAD2jsu9EtIlm+1gNB8aUPiIQsDClxNJJ73+CIOBaWaXHsA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR04MB3877 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200214_184104_295060_0E16D5F0 X-CRM114-Status: GOOD ( 15.95 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anup Patel , Paul Walmsley Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org On 2020/02/15 11:26, Sean Anderson wrote:=0A= > On 2/14/20 9:15 PM, Damien Le Moal wrote:=0A= >> On 2020/02/15 5:18, Sean Anderson wrote:=0A= >>> Hi,=0A= >>>=0A= >>> On 2/12/20 5:34 AM, Damien Le Moal wrote:=0A= >>>> Compilation errors trigger if ARCH_SPARSEMEM_ENABLE is enabled for=0A= >>>> a nommu kernel. Since the sparsemem model does not make sense anyway= =0A= >>>> for the nommu case, do not allow selecting this option to always use= =0A= >>>> the flatmem model.=0A= >>>>=0A= >>>> Signed-off-by: Damien Le Moal =0A= >>>> ---=0A= >>>> arch/riscv/Kconfig | 1 +=0A= >>>> 1 file changed, 1 insertion(+)=0A= >>>>=0A= >>>> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig=0A= >>>> index 73f029eae0cc..1a3b5a5276be 100644=0A= >>>> --- a/arch/riscv/Kconfig=0A= >>>> +++ b/arch/riscv/Kconfig=0A= >>>> @@ -121,6 +121,7 @@ config ARCH_FLATMEM_ENABLE=0A= >>>> =0A= >>>> config ARCH_SPARSEMEM_ENABLE=0A= >>>> def_bool y=0A= >>>> + depends on MMU=0A= >>>> select SPARSEMEM_VMEMMAP_ENABLE=0A= >>>> =0A= >>>> config ARCH_SELECT_MEMORY_MODEL=0A= >>>>=0A= >>>=0A= >>> Just for some background, why did you choose NOMMU? Afaik the K210 has= =0A= >>> an MMU following the RISC-V privileged specification 1.9=0A= >>=0A= >> Our early experiments with the k210 with opensbi revealed that the mmu i= s=0A= >> definitely not a normal one or that it is not functional (e.g. S-mode fa= ult=0A= >> delegation bit setup leads to a hang). So at the time, we started assumi= ng=0A= >> that this is a nommu platform.=0A= >>=0A= >> Since then, others also mentioned that there is in fact an MMU but not= =0A= >> following the latest specs (I think Olof mentioned that). But I have not= =0A= >> look into this (yet) to try to make it work. Not sure how much effort wo= uld=0A= >> be needed on the kernel to support this older specs mmu.=0A= >>=0A= >> In any case, considering the tiny 6+2MB of memory available, direct M-mo= de=0A= >> Linux boot avoids the bootloader chain and openSBI use, which saves a lo= t=0A= >> of memory. We could reduce this chain to opensbi with direct payload onl= y,=0A= >> but even then, page alignment will lead to memory loss. And at run-time,= =0A= >> nommu saves a lot too with the absence of page tables. Nommu makes sense= =0A= >> for this platform.=0A= > =0A= > Well, the VM mode bits are in mstatus for this priv spec, so OpenSBI=0A= > won't work since there is no way to set them. =0A= =0A= Interesting. At FOSDEM, we discussed with Palmer the work that would be=0A= needed to disentangle NOMMU and M-MODE boot, which for now are rather=0A= synonymous, but shouldn't. I guess this platform would still require M-MODE= =0A= boot, but not necessarily NOMMU.=0A= =0A= >> This is the first step to get this platform running Linux. Due to the lo= w=0A= >> memory, it probably isn't a practical use case to use Linux in the first= =0A= >> place, but it definitely is a great inexpensive platform for getting=0A= >> started with RISCV. NOMMU allows running Linux without much effort. Goin= g=0A= >> forward, we can also try to get that SoC MMU running.=0A= > =0A= > Yeah, that's pretty reasonable. However, I don't think much has changed= =0A= > other than the locations of some of the registers has been changed=0A= > around. The existing code to set up page table entries should not need=0A= > major modifications.=0A= =0A= OK. Sounds easy enough. But I think cleanup work to dissociate M-mode boot= =0A= and NOMMU will be needed first. After that, trying to enable the MMU should= =0A= be easier.=0A= =0A= > =0A= > Alternatively, the base+bound scheme could probably work pretty well=0A= > with low memory, though we would not be able to re-use any existing=0A= > code.=0A= > =0A= > --Sean=0A= > =0A= =0A= =0A= -- =0A= Damien Le Moal=0A= Western Digital Research=0A=