Re: [Intel-wired-lan] [net-next PATCH 1/7] ice: implement adjfine with mul_u64_u64_div_u64

["G, GurucharanX" <gurucharanx.g@intel.com>]

> -----Original Message-----
> From: Intel-wired-lan <intel-wired-lan-bounces@osuosl.org> On Behalf Of
> Jacob Keller
> Sent: Friday, July 22, 2022 3:00 AM
> To: Intel Wired LAN <intel-wired-lan@lists.osuosl.org>
> Subject: [Intel-wired-lan] [net-next PATCH 1/7] ice: implement adjfine with
> mul_u64_u64_div_u64
> 
> The PTP frequency adjustment code needs to determine an appropriate
> adjustment given an input scaled_ppm adjustment.
> 
> We calculate the adjustment to the register by multiplying the base
> (nominal) increment value by the scaled_ppm and then dividing by the
> scaled one million value.
> 
> For very large adjustments, this might overflow. To avoid this, both the
> scaled_ppm and divisor values are downshifted.
> 
> We can avoid that on X86 architectures by using mul_u64_u64_div_u64. This
> helper function will perform the multiplication and division with 128bit
> intermediate values. We know that scaled_ppm is never larger than the
> divisor so this operation will never result in an overflow.
> 
> This improves the accuracy of the calculations for large adjustment values on
> X86. It is likely an improvement on other architectures as well because the
> default implementation of mul_u64_u64_div_u64 is smarter than the original
> approach taken in the ice code.
> 
> Additionally, this implementation is easier to read, using fewer local variables
> and lines of code to implement.
> 
> Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
> ---
>  drivers/net/ethernet/intel/ice/ice_ptp.c | 16 +++-------------
>  1 file changed, 3 insertions(+), 13 deletions(-)
> 

Tested-by: Gurucharan <gurucharanx.g@intel.com> (A Contingent worker at Intel)
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