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boundary="===============0661162508==" Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" --===============0661162508== Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_BYAPR12MB28401B53159CAC8ECF5B2322F42D9BYAPR12MB2840namp_" --_000_BYAPR12MB28401B53159CAC8ECF5B2322F42D9BYAPR12MB2840namp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable [AMD Public Use] I dont think the pp_nodes expose the vclk dclk nodes, but it might be bette= r to rework this patch to expose those instead, and just add the voltages..= . ________________________________ From: Lazar, Lijo Sent: Sunday, May 16, 2021 11:28 PM To: Nieto, David M ; amd-gfx@lists.freedesktop.org Cc: Nieto, David M Subject: RE: [PATCH 2/2] drm/amdgpu/pm: add new fields for Navi1x [AMD Public Use] Metrics table carries dynamic state information of the ASIC. There are othe= r pp_* nodes which carry static information about min/max and levels suppor= ted and that is a one-time query. Why there is a need to put everything in = metrics data? Thanks, Lijo -----Original Message----- From: amd-gfx On Behalf Of David M = Nieto Sent: Saturday, May 15, 2021 2:32 AM To: amd-gfx@lists.freedesktop.org Cc: Nieto, David M Subject: [PATCH 2/2] drm/amdgpu/pm: add new fields for Navi1x Fill voltage and frequency ranges fields Signed-off-by: David M Nieto Change-Id: I07f926dea46e80a96e1c972ba9dbc804b812d503 --- .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 434 +++++++++++++++++- 1 file changed, 417 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/= drm/amd/pm/swsmu/smu11/navi10_ppt.c index ac13042672ea..a412fa9a95ec 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c @@ -505,7 +505,7 @@ static int navi10_tables_init(struct smu_context *smu) goto err0_out; smu_table->metrics_time =3D 0; - smu_table->gpu_metrics_table_size =3D sizeof(struct gpu_metrics_v1_= 1); + smu_table->gpu_metrics_table_size =3D sizeof(struct gpu_metrics_v1_= 3); smu_table->gpu_metrics_table =3D kzalloc(smu_table->gpu_metrics_ta= ble_size, GFP_KERNEL); if (!smu_table->gpu_metrics_table) goto err1_out; @@ -2627,10 +2627,11 @@ static ssize_t navi10_get_legacy_gpu_metrics(struct= smu_context *smu, void **table) { struct smu_table_context *smu_table =3D &smu->smu_table; - struct gpu_metrics_v1_1 *gpu_metrics =3D - (struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table; + struct gpu_metrics_v1_3 *gpu_metrics =3D + (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; SmuMetrics_legacy_t metrics; int ret =3D 0; + int freq =3D 0, dpm =3D 0; mutex_lock(&smu->metrics_lock); @@ -2646,7 +2647,7 @@ static ssize_t navi10_get_legacy_gpu_metrics(struct s= mu_context *smu, mutex_unlock(&smu->metrics_lock); - smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 1); + smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); gpu_metrics->temperature_edge =3D metrics.TemperatureEdge; gpu_metrics->temperature_hotspot =3D metrics.TemperatureHotspot; @= @ -2681,19 +2682,119 @@ static ssize_t navi10_get_legacy_gpu_metrics(struct= smu_context *smu, gpu_metrics->system_clock_counter =3D ktime_get_boottime_ns(); + gpu_metrics->voltage_gfx =3D (155000 - 625 * metrics.CurrGfxVoltage= Offset) / 100; + gpu_metrics->voltage_mem =3D (155000 - 625 * metrics.CurrMemVidOffs= et) / 100; + gpu_metrics->voltage_soc =3D (155000 - 625 * +metrics.CurrSocVoltageOffset) / 100; + + gpu_metrics->max_socket_power =3D smu->power_limit; + + /* Frequency and DPM ranges */ + + ret =3D smu_v11_0_get_dpm_freq_by_index(smu, SMU_GFXCLK, 0, &freq); + if (ret) + goto out; + gpu_metrics->min_gfxclk_frequency =3D freq; + + ret =3D smu_v11_0_get_dpm_freq_by_index(smu, SMU_SOCCLK, 0, &freq); + if (ret) + goto out; + gpu_metrics->min_socclk_frequency =3D freq; + + ret =3D smu_v11_0_get_dpm_freq_by_index(smu, SMU_UCLK, 0, &freq); + if (ret) + goto out; + gpu_metrics->min_uclk_frequency =3D freq; + + ret =3D smu_v11_0_get_dpm_freq_by_index(smu, SMU_VCLK, 0, &freq); + if (ret) + goto out; + gpu_metrics->min_vclk0_frequency =3D freq; + + ret =3D smu_v11_0_get_dpm_freq_by_index(smu, SMU_DCLK, 0, &freq); + if (ret) + goto out; + gpu_metrics->min_dclk0_frequency =3D freq; + + ret =3D smu_v11_0_get_dpm_level_count(smu, SMU_GFXCLK, &dpm); + if (ret) + goto out; + gpu_metrics->max_gfxclk_dpm =3D dpm; + + ret =3D smu_v11_0_get_dpm_freq_by_index(smu, SMU_GFXCLK, + gpu_metrics->max_gfxclk_dpm - 1, &freq); + if (ret) + goto out; + + gpu_metrics->max_gfxclk_frequency =3D freq; + + ret =3D smu_v11_0_get_dpm_level_count(smu, SMU_SOCCLK, &dpm); + if (ret) + goto out; + + gpu_metrics->max_socclk_dpm =3D dpm; + + ret =3D smu_v11_0_get_dpm_freq_by_index(smu, SMU_SOCCLK, + gpu_metrics->max_socclk_dpm - 1, &freq); + if (ret) + goto out; + + gpu_metrics->max_socclk_frequency =3D freq; + + ret =3D smu_v11_0_get_dpm_level_count(smu, SMU_UCLK, &dpm); + if (ret) + goto out; + + gpu_metrics->max_uclk_dpm =3D dpm; + + ret =3D smu_v11_0_get_dpm_freq_by_index(smu, SMU_UCLK, + gpu_metrics->max_uclk_dpm - 1, &freq); + if (ret) + goto out; + + gpu_metrics->max_uclk_frequency =3D freq; + + ret =3D smu_v11_0_get_dpm_level_count(smu, SMU_VCLK, &dpm); + if (ret) + goto out; + + gpu_metrics->max_vclk0_dpm =3D dpm; + + ret =3D smu_v11_0_get_dpm_freq_by_index(smu, SMU_VCLK, + gpu_metrics->max_vclk0_dpm - 1, &freq); + if (ret) + goto out; + + gpu_metrics->max_vclk0_frequency =3D freq; + + ret =3D smu_v11_0_get_dpm_level_count(smu, SMU_DCLK, &dpm); + if (ret) + goto out; + + gpu_metrics->max_dclk0_dpm =3D dpm; + + ret =3D smu_v11_0_get_dpm_freq_by_index(smu, SMU_DCLK, + gpu_metrics->max_dclk0_dpm - 1, &freq); + if (ret) + goto out; + + gpu_metrics->max_dclk0_frequency =3D freq; + *table =3D (void *)gpu_metrics; - return sizeof(struct gpu_metrics_v1_1); + return sizeof(struct gpu_metrics_v1_3); +out: + return ret; } static ssize_t navi10_get_gpu_metrics(struct smu_context *smu, void **table) { struct smu_table_context *smu_table =3D &smu->smu_table; - struct gpu_metrics_v1_1 *gpu_metrics =3D - (struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table; + struct gpu_metrics_v1_3 *gpu_metrics =3D + (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; SmuMetrics_t metrics; int ret =3D 0; + int freq =3D 0, dpm =3D 0; mutex_lock(&smu->metrics_lock); @@ -2709,7 +2810,7 @@ static ssize_t navi10_get_gpu_metrics(struct smu_cont= ext *smu, mutex_unlock(&smu->metrics_lock); - smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 1); + smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); gpu_metrics->temperature_edge =3D metrics.TemperatureEdge; gpu_metrics->temperature_hotspot =3D metrics.TemperatureHotspot; @= @ -2746,19 +2847,119 @@ static ssize_t navi10_get_gpu_metrics(struct smu_co= ntext *smu, gpu_metrics->system_clock_counter =3D ktime_get_boottime_ns(); + gpu_metrics->voltage_gfx =3D (155000 - 625 * metrics.CurrGfxVoltage= Offset) / 100; + gpu_metrics->voltage_mem =3D (155000 - 625 * metrics.CurrMemVidOffs= et) / 100; + gpu_metrics->voltage_soc =3D (155000 - 625 * +metrics.CurrSocVoltageOffset) / 100; + + gpu_metrics->max_socket_power =3D smu->power_limit; + + /* Frequency and DPM ranges */ + + ret =3D smu_v11_0_get_dpm_freq_by_index(smu, SMU_GFXCLK, 0, &freq); + if (ret) + goto out; + gpu_metrics->min_gfxclk_frequency =3D freq; + + ret =3D smu_v11_0_get_dpm_freq_by_index(smu, SMU_SOCCLK, 0, &freq); + if (ret) + goto out; + gpu_metrics->min_socclk_frequency =3D freq; + + ret =3D smu_v11_0_get_dpm_freq_by_index(smu, SMU_UCLK, 0, &freq); + if (ret) + goto out; + gpu_metrics->min_uclk_frequency =3D freq; + + ret =3D smu_v11_0_get_dpm_freq_by_index(smu, SMU_VCLK, 0, &freq); + if (ret) + goto out; + gpu_metrics->min_vclk0_frequency =3D freq; + + ret =3D smu_v11_0_get_dpm_freq_by_index(smu, SMU_DCLK, 0, &freq); + if (ret) + goto out; + gpu_metrics->min_dclk0_frequency =3D freq; + + ret =3D smu_v11_0_get_dpm_level_count(smu, SMU_GFXCLK, &dpm); + if (ret) + goto out; + gpu_metrics->max_gfxclk_dpm =3D dpm; + + ret =3D smu_v11_0_get_dpm_freq_by_index(smu, SMU_GFXCLK, + gpu_metrics->max_gfxclk_dpm - 1, &freq); + if (ret) + goto out; + + gpu_metrics->max_gfxclk_frequency =3D freq; + + ret =3D smu_v11_0_get_dpm_level_count(smu, SMU_SOCCLK, &dpm); + if (ret) + goto out; + + gpu_metrics->max_socclk_dpm =3D dpm; + + ret =3D smu_v11_0_get_dpm_freq_by_index(smu, SMU_SOCCLK, + gpu_metrics->max_socclk_dpm - 1, &freq); + if (ret) + goto out; + + gpu_metrics->max_socclk_frequency =3D freq; + + ret =3D smu_v11_0_get_dpm_level_count(smu, SMU_UCLK, &dpm); + if (ret) + goto out; + + gpu_metrics->max_uclk_dpm =3D dpm; + + ret =3D smu_v11_0_get_dpm_freq_by_index(smu, SMU_UCLK, + gpu_metrics->max_uclk_dpm - 1, &freq); + if (ret) + goto out; + + gpu_metrics->max_uclk_frequency =3D freq; + + ret =3D smu_v11_0_get_dpm_level_count(smu, SMU_VCLK, &dpm); + if (ret) + goto out; + + gpu_metrics->max_vclk0_dpm =3D dpm; + + ret =3D smu_v11_0_get_dpm_freq_by_index(smu, SMU_VCLK, + gpu_metrics->max_vclk0_dpm - 1, &freq); + if (ret) + goto out; + + gpu_metrics->max_vclk0_frequency =3D freq; + + ret =3D smu_v11_0_get_dpm_level_count(smu, SMU_DCLK, &dpm); + if (ret) + goto out; + + gpu_metrics->max_dclk0_dpm =3D dpm; + + ret =3D smu_v11_0_get_dpm_freq_by_index(smu, SMU_DCLK, + gpu_metrics->max_dclk0_dpm - 1, &freq); + if (ret) + goto out; + + gpu_metrics->max_dclk0_frequency =3D freq; + *table =3D (void *)gpu_metrics; - return sizeof(struct gpu_metrics_v1_1); + return sizeof(struct gpu_metrics_v1_3); +out: + return ret; } static ssize_t navi12_get_legacy_gpu_metrics(struct smu_context *smu, void **table) { struct smu_table_context *smu_table =3D &smu->smu_table; - struct gpu_metrics_v1_1 *gpu_metrics =3D - (struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table; + struct gpu_metrics_v1_3 *gpu_metrics =3D + (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; SmuMetrics_NV12_legacy_t metrics; int ret =3D 0; + int freq =3D 0, dpm =3D 0; mutex_lock(&smu->metrics_lock); @@ -2774,7 +2975,7 @@ static ssize_t navi12_get_legacy_gpu_metrics(struct s= mu_context *smu, mutex_unlock(&smu->metrics_lock); - smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 1); + smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); gpu_metrics->temperature_edge =3D metrics.TemperatureEdge; gpu_metrics->temperature_hotspot =3D metrics.TemperatureHotspot; @= @ -2814,19 +3015,119 @@ static ssize_t navi12_get_legacy_gpu_metrics(struct= smu_context *smu, gpu_metrics->system_clock_counter =3D ktime_get_boottime_ns(); + gpu_metrics->voltage_gfx =3D (155000 - 625 * metrics.CurrGfxVoltage= Offset) / 100; + gpu_metrics->voltage_mem =3D (155000 - 625 * metrics.CurrMemVidOffs= et) / 100; + gpu_metrics->voltage_soc =3D (155000 - 625 * +metrics.CurrSocVoltageOffset) / 100; + + gpu_metrics->max_socket_power =3D smu->power_limit; + + /* Frequency and DPM ranges */ + + ret =3D smu_v11_0_get_dpm_freq_by_index(smu, SMU_GFXCLK, 0, &freq); + if (ret) + goto out; + gpu_metrics->min_gfxclk_frequency =3D freq; + + ret =3D smu_v11_0_get_dpm_freq_by_index(smu, SMU_SOCCLK, 0, &freq); + if (ret) + goto out; + gpu_metrics->min_socclk_frequency =3D freq; + + ret =3D smu_v11_0_get_dpm_freq_by_index(smu, SMU_UCLK, 0, &freq); + if (ret) + goto out; + gpu_metrics->min_uclk_frequency =3D freq; + + ret =3D smu_v11_0_get_dpm_freq_by_index(smu, SMU_VCLK, 0, &freq); + if (ret) + goto out; + gpu_metrics->min_vclk0_frequency =3D freq; + + ret =3D smu_v11_0_get_dpm_freq_by_index(smu, SMU_DCLK, 0, &freq); + if (ret) + goto out; + gpu_metrics->min_dclk0_frequency =3D freq; + + ret =3D smu_v11_0_get_dpm_level_count(smu, SMU_GFXCLK, &dpm); + if (ret) + goto out; + gpu_metrics->max_gfxclk_dpm =3D dpm; + + ret =3D smu_v11_0_get_dpm_freq_by_index(smu, SMU_GFXCLK, + gpu_metrics->max_gfxclk_dpm - 1, &freq); + if (ret) + goto out; + + gpu_metrics->max_gfxclk_frequency =3D freq; + + ret =3D smu_v11_0_get_dpm_level_count(smu, SMU_SOCCLK, &dpm); + if (ret) + goto out; + + gpu_metrics->max_socclk_dpm =3D dpm; + + ret =3D smu_v11_0_get_dpm_freq_by_index(smu, SMU_SOCCLK, + gpu_metrics->max_socclk_dpm - 1, &freq); + if (ret) + goto out; + + gpu_metrics->max_socclk_frequency =3D freq; + + ret =3D smu_v11_0_get_dpm_level_count(smu, SMU_UCLK, &dpm); + if (ret) + goto out; + + gpu_metrics->max_uclk_dpm =3D dpm; + + ret =3D smu_v11_0_get_dpm_freq_by_index(smu, SMU_UCLK, + gpu_metrics->max_uclk_dpm - 1, &freq); + if (ret) + goto out; + + gpu_metrics->max_uclk_frequency =3D freq; + + ret =3D smu_v11_0_get_dpm_level_count(smu, SMU_VCLK, &dpm); + if (ret) + goto out; + + gpu_metrics->max_vclk0_dpm =3D dpm; + + ret =3D smu_v11_0_get_dpm_freq_by_index(smu, SMU_VCLK, + gpu_metrics->max_vclk0_dpm - 1, &freq); + if (ret) + goto out; + + gpu_metrics->max_vclk0_frequency =3D freq; + + ret =3D smu_v11_0_get_dpm_level_count(smu, SMU_DCLK, &dpm); + if (ret) + goto out; + + gpu_metrics->max_dclk0_dpm =3D dpm; + + ret =3D smu_v11_0_get_dpm_freq_by_index(smu, SMU_DCLK, + gpu_metrics->max_dclk0_dpm - 1, &freq); + if (ret) + goto out; + + gpu_metrics->max_dclk0_frequency =3D freq; + *table =3D (void *)gpu_metrics; - return sizeof(struct gpu_metrics_v1_1); + return sizeof(struct gpu_metrics_v1_3); +out: + return ret; } static ssize_t navi12_get_gpu_metrics(struct smu_context *smu, void **table) { struct smu_table_context *smu_table =3D &smu->smu_table; - struct gpu_metrics_v1_1 *gpu_metrics =3D - (struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table; + struct gpu_metrics_v1_3 *gpu_metrics =3D + (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; SmuMetrics_NV12_t metrics; int ret =3D 0; + int freq =3D 0, dpm =3D 0; mutex_lock(&smu->metrics_lock); @@ -2842,7 +3143,7 @@ static ssize_t navi12_get_gpu_metrics(struct smu_cont= ext *smu, mutex_unlock(&smu->metrics_lock); - smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 1); + smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); gpu_metrics->temperature_edge =3D metrics.TemperatureEdge; gpu_metrics->temperature_hotspot =3D metrics.TemperatureHotspot; @= @ -2884,9 +3185,108 @@ static ssize_t navi12_get_gpu_metrics(struct smu_con= text *smu, gpu_metrics->system_clock_counter =3D ktime_get_boottime_ns(); + gpu_metrics->voltage_gfx =3D (155000 - 625 * metrics.CurrGfxVoltage= Offset) / 100; + gpu_metrics->voltage_mem =3D (155000 - 625 * metrics.CurrMemVidOffs= et) / 100; + gpu_metrics->voltage_soc =3D (155000 - 625 * +metrics.CurrSocVoltageOffset) / 100; + + gpu_metrics->max_socket_power =3D smu->power_limit; + + /* Frequency and DPM ranges */ + + ret =3D smu_v11_0_get_dpm_freq_by_index(smu, SMU_GFXCLK, 0, &freq); + if (ret) + goto out; + gpu_metrics->min_gfxclk_frequency =3D freq; + + ret =3D smu_v11_0_get_dpm_freq_by_index(smu, SMU_SOCCLK, 0, &freq); + if (ret) + goto out; + gpu_metrics->min_socclk_frequency =3D freq; + + ret =3D smu_v11_0_get_dpm_freq_by_index(smu, SMU_UCLK, 0, &freq); + if (ret) + goto out; + gpu_metrics->min_uclk_frequency =3D freq; + + ret =3D smu_v11_0_get_dpm_freq_by_index(smu, SMU_VCLK, 0, &freq); + if (ret) + goto out; + gpu_metrics->min_vclk0_frequency =3D freq; + + ret =3D smu_v11_0_get_dpm_freq_by_index(smu, SMU_DCLK, 0, &freq); + if (ret) + goto out; + gpu_metrics->min_dclk0_frequency =3D freq; + + ret =3D smu_v11_0_get_dpm_level_count(smu, SMU_GFXCLK, &dpm); + if (ret) + goto out; + gpu_metrics->max_gfxclk_dpm =3D dpm; + + ret =3D smu_v11_0_get_dpm_freq_by_index(smu, SMU_GFXCLK, + gpu_metrics->max_gfxclk_dpm - 1, &freq); + if (ret) + goto out; + + gpu_metrics->max_gfxclk_frequency =3D freq; + + ret =3D smu_v11_0_get_dpm_level_count(smu, SMU_SOCCLK, &dpm); + if (ret) + goto out; + + gpu_metrics->max_socclk_dpm =3D dpm; + + ret =3D smu_v11_0_get_dpm_freq_by_index(smu, SMU_SOCCLK, + gpu_metrics->max_socclk_dpm - 1, &freq); + if (ret) + goto out; + + gpu_metrics->max_socclk_frequency =3D freq; + + ret =3D smu_v11_0_get_dpm_level_count(smu, SMU_UCLK, &dpm); + if (ret) + goto out; + + gpu_metrics->max_uclk_dpm =3D dpm; + + ret =3D smu_v11_0_get_dpm_freq_by_index(smu, SMU_UCLK, + gpu_metrics->max_uclk_dpm - 1, &freq); + if (ret) + goto out; + + gpu_metrics->max_uclk_frequency =3D freq; + + ret =3D smu_v11_0_get_dpm_level_count(smu, SMU_VCLK, &dpm); + if (ret) + goto out; + + gpu_metrics->max_vclk0_dpm =3D dpm; + + ret =3D smu_v11_0_get_dpm_freq_by_index(smu, SMU_VCLK, + gpu_metrics->max_vclk0_dpm - 1, &freq); + if (ret) + goto out; + + gpu_metrics->max_vclk0_frequency =3D freq; + + ret =3D smu_v11_0_get_dpm_level_count(smu, SMU_DCLK, &dpm); + if (ret) + goto out; + + gpu_metrics->max_dclk0_dpm =3D dpm; + + ret =3D smu_v11_0_get_dpm_freq_by_index(smu, SMU_DCLK, + gpu_metrics->max_dclk0_dpm - 1, &freq); + if (ret) + goto out; + + gpu_metrics->max_dclk0_frequency =3D freq; + *table =3D (void *)gpu_metrics; - return sizeof(struct gpu_metrics_v1_1); + return sizeof(struct gpu_metrics_v1_3); +out: + return ret; } static ssize_t navi1x_get_gpu_metrics(struct smu_context *smu, -- 2.17.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2Flists.f= reedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=3D04%7C01%7Clijo.laz= ar%40amd.com%7C2aabcce1455c410dec6008d9171b80a8%7C3dd8961fe4884e608e11a82d9= 94e183d%7C0%7C0%7C637566229187346163%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLj= AwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=3DNgH= qow7Ra1rXTqz4suB8Vv%2FASOYRRJAtCgLUcpHRDto%3D&reserved=3D0 --_000_BYAPR12MB28401B53159CAC8ECF5B2322F42D9BYAPR12MB2840namp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

[AMD Public Use]


I dont think the pp_nodes expose the vclk dclk nodes, but it might be bette= r to rework this patch to expose those instead, and just add the voltages..= .
From: Lazar, Lijo <Lijo.= Lazar@amd.com>
Sent: Sunday, May 16, 2021 11:28 PM
To: Nieto, David M <David.Nieto@amd.com>; amd-gfx@lists.freede= sktop.org <amd-gfx@lists.freedesktop.org>
Cc: Nieto, David M <David.Nieto@amd.com>
Subject: RE: [PATCH 2/2] drm/amdgpu/pm: add new fields for Navi1x
 
[AMD Public Use]

Metrics table carries dynamic state information of the ASIC. There are othe= r pp_* nodes which carry static information about min/max and levels suppor= ted and that is a one-time query. Why there is a need to put everything in = metrics data?

Thanks,
Lijo

-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Da= vid M Nieto
Sent: Saturday, May 15, 2021 2:32 AM
To: amd-gfx@lists.freedesktop.org
Cc: Nieto, David M <David.Nieto@amd.com>
Subject: [PATCH 2/2] drm/amdgpu/pm: add new fields for Navi1x

Fill voltage and frequency ranges fields

Signed-off-by: David M Nieto <david.nieto@amd.com>
Change-Id: I07f926dea46e80a96e1c972ba9dbc804b812d503
---
 .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c   | 434 +++++++= ++++++++++-
 1 file changed, 417 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/= drm/amd/pm/swsmu/smu11/navi10_ppt.c
index ac13042672ea..a412fa9a95ec 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -505,7 +505,7 @@ static int navi10_tables_init(struct smu_context *smu)<= br>             &nb= sp;    goto err0_out;
         smu_table->metrics_time= =3D 0;
 
-       smu_table->gpu_metrics_table_size = =3D sizeof(struct gpu_metrics_v1_1);
+       smu_table->gpu_metrics_table_size = =3D sizeof(struct gpu_metrics_v1_3);
         smu_table->gpu_metrics_= table =3D kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
         if (!smu_table->gpu_met= rics_table)
            &nb= sp;    goto err1_out;
@@ -2627,10 +2627,11 @@ static ssize_t navi10_get_legacy_gpu_metrics(struct= smu_context *smu,
            &nb= sp;            =             &nb= sp;        void **table)
 {
         struct smu_table_context *= smu_table =3D &smu->smu_table;
-       struct gpu_metrics_v1_1 *gpu_metrics = =3D
-            &n= bsp;  (struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table;
+       struct gpu_metrics_v1_3 *gpu_metrics = =3D
+            &n= bsp;  (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
         SmuMetrics_legacy_t metric= s;
         int ret =3D 0;
+       int freq =3D 0, dpm =3D 0;
 
         mutex_lock(&smu->me= trics_lock);
 
@@ -2646,7 +2647,7 @@ static ssize_t navi10_get_legacy_gpu_metrics(struct s= mu_context *smu,
 
         mutex_unlock(&smu->= metrics_lock);
 
-       smu_cmn_init_soft_gpu_metrics(gpu_met= rics, 1, 1);
+       smu_cmn_init_soft_gpu_metrics(gpu_met= rics, 1, 3);
 
         gpu_metrics->temperatur= e_edge =3D metrics.TemperatureEdge;
         gpu_metrics->temperatur= e_hotspot =3D metrics.TemperatureHotspot; @@ -2681,19 +2682,119 @@ static s= size_t navi10_get_legacy_gpu_metrics(struct smu_context *smu,
 
         gpu_metrics->system_clo= ck_counter =3D ktime_get_boottime_ns();
 
+       gpu_metrics->voltage_gfx =3D (1550= 00 - 625 * metrics.CurrGfxVoltageOffset) / 100;
+       gpu_metrics->voltage_mem =3D (1550= 00 - 625 * metrics.CurrMemVidOffset) / 100;
+       gpu_metrics->voltage_soc =3D (1550= 00 - 625 *
+metrics.CurrSocVoltageOffset) / 100;
+
+       gpu_metrics->max_socket_power =3D = smu->power_limit;
+
+       /* Frequency and DPM ranges */
+
+       ret =3D smu_v11_0_get_dpm_freq_by_ind= ex(smu, SMU_GFXCLK, 0, &freq);
+       if (ret)
+            &n= bsp;  goto out;
+       gpu_metrics->min_gfxclk_frequency = =3D freq;
+
+       ret =3D smu_v11_0_get_dpm_freq_by_ind= ex(smu, SMU_SOCCLK, 0, &freq);
+       if (ret)
+            &n= bsp;  goto out;
+       gpu_metrics->min_socclk_frequency = =3D freq;
+
+       ret =3D smu_v11_0_get_dpm_freq_by_ind= ex(smu, SMU_UCLK, 0, &freq);
+       if (ret)
+            &n= bsp;  goto out;
+       gpu_metrics->min_uclk_frequency = =3D freq;
+
+       ret =3D smu_v11_0_get_dpm_freq_by_ind= ex(smu, SMU_VCLK, 0, &freq);
+       if (ret)
+            &n= bsp;  goto out;
+       gpu_metrics->min_vclk0_frequency = =3D freq;
+
+       ret =3D smu_v11_0_get_dpm_freq_by_ind= ex(smu, SMU_DCLK, 0, &freq);
+       if (ret)
+            &n= bsp;  goto out;
+       gpu_metrics->min_dclk0_frequency = =3D freq;
+
+       ret =3D smu_v11_0_get_dpm_level_count= (smu, SMU_GFXCLK, &dpm);
+       if (ret)
+            &n= bsp;  goto out;
+       gpu_metrics->max_gfxclk_dpm =3D dp= m;
+
+       ret =3D smu_v11_0_get_dpm_freq_by_ind= ex(smu, SMU_GFXCLK,
+            &n= bsp;          gpu_metrics->= max_gfxclk_dpm - 1, &freq);
+       if (ret)
+            &n= bsp;  goto out;
+
+       gpu_metrics->max_gfxclk_frequency = =3D freq;
+
+       ret =3D smu_v11_0_get_dpm_level_count= (smu, SMU_SOCCLK, &dpm);
+       if (ret)
+            &n= bsp;  goto out;
+
+       gpu_metrics->max_socclk_dpm =3D dp= m;
+
+       ret =3D smu_v11_0_get_dpm_freq_by_ind= ex(smu, SMU_SOCCLK,
+            &n= bsp;          gpu_metrics->= max_socclk_dpm - 1, &freq);
+       if (ret)
+            &n= bsp;  goto out;
+
+       gpu_metrics->max_socclk_frequency = =3D freq;
+
+       ret =3D smu_v11_0_get_dpm_level_count= (smu, SMU_UCLK, &dpm);
+       if (ret)
+            &n= bsp;  goto out;
+
+       gpu_metrics->max_uclk_dpm =3D dpm;=
+
+       ret =3D smu_v11_0_get_dpm_freq_by_ind= ex(smu, SMU_UCLK,
+            &n= bsp;          gpu_metrics->= max_uclk_dpm - 1, &freq);
+       if (ret)
+            &n= bsp;  goto out;
+
+       gpu_metrics->max_uclk_frequency = =3D freq;
+
+       ret =3D smu_v11_0_get_dpm_level_count= (smu, SMU_VCLK, &dpm);
+       if (ret)
+            &n= bsp;  goto out;
+
+       gpu_metrics->max_vclk0_dpm =3D dpm= ;
+
+       ret =3D smu_v11_0_get_dpm_freq_by_ind= ex(smu, SMU_VCLK,
+            &n= bsp;          gpu_metrics->= max_vclk0_dpm - 1, &freq);
+       if (ret)
+            &n= bsp;  goto out;
+
+       gpu_metrics->max_vclk0_frequency = =3D freq;
+
+       ret =3D smu_v11_0_get_dpm_level_count= (smu, SMU_DCLK, &dpm);
+       if (ret)
+            &n= bsp;  goto out;
+
+       gpu_metrics->max_dclk0_dpm =3D dpm= ;
+
+       ret =3D smu_v11_0_get_dpm_freq_by_ind= ex(smu, SMU_DCLK,
+            &n= bsp;          gpu_metrics->= max_dclk0_dpm - 1, &freq);
+       if (ret)
+            &n= bsp;  goto out;
+
+       gpu_metrics->max_dclk0_frequency = =3D freq;
+
         *table =3D (void *)gpu_met= rics;
 
-       return sizeof(struct gpu_metrics_v1_1= );
+       return sizeof(struct gpu_metrics_v1_3= );
+out:
+       return ret;
 }
 
 static ssize_t navi10_get_gpu_metrics(struct smu_context *smu,
            &nb= sp;            =             &nb= sp; void **table)
 {
         struct smu_table_context *= smu_table =3D &smu->smu_table;
-       struct gpu_metrics_v1_1 *gpu_metrics = =3D
-            &n= bsp;  (struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table;
+       struct gpu_metrics_v1_3 *gpu_metrics = =3D
+            &n= bsp;  (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
         SmuMetrics_t metrics;
         int ret =3D 0;
+       int freq =3D 0, dpm =3D 0;
 
         mutex_lock(&smu->me= trics_lock);
 
@@ -2709,7 +2810,7 @@ static ssize_t navi10_get_gpu_metrics(struct smu_cont= ext *smu,
 
         mutex_unlock(&smu->= metrics_lock);
 
-       smu_cmn_init_soft_gpu_metrics(gpu_met= rics, 1, 1);
+       smu_cmn_init_soft_gpu_metrics(gpu_met= rics, 1, 3);
 
         gpu_metrics->temperatur= e_edge =3D metrics.TemperatureEdge;
         gpu_metrics->temperatur= e_hotspot =3D metrics.TemperatureHotspot; @@ -2746,19 +2847,119 @@ static s= size_t navi10_get_gpu_metrics(struct smu_context *smu,
 
         gpu_metrics->system_clo= ck_counter =3D ktime_get_boottime_ns();
 
+       gpu_metrics->voltage_gfx =3D (1550= 00 - 625 * metrics.CurrGfxVoltageOffset) / 100;
+       gpu_metrics->voltage_mem =3D (1550= 00 - 625 * metrics.CurrMemVidOffset) / 100;
+       gpu_metrics->voltage_soc =3D (1550= 00 - 625 *
+metrics.CurrSocVoltageOffset) / 100;
+
+       gpu_metrics->max_socket_power =3D = smu->power_limit;
+
+       /* Frequency and DPM ranges */
+
+       ret =3D smu_v11_0_get_dpm_freq_by_ind= ex(smu, SMU_GFXCLK, 0, &freq);
+       if (ret)
+            &n= bsp;  goto out;
+       gpu_metrics->min_gfxclk_frequency = =3D freq;
+
+       ret =3D smu_v11_0_get_dpm_freq_by_ind= ex(smu, SMU_SOCCLK, 0, &freq);
+       if (ret)
+            &n= bsp;  goto out;
+       gpu_metrics->min_socclk_frequency = =3D freq;
+
+       ret =3D smu_v11_0_get_dpm_freq_by_ind= ex(smu, SMU_UCLK, 0, &freq);
+       if (ret)
+            &n= bsp;  goto out;
+       gpu_metrics->min_uclk_frequency = =3D freq;
+
+       ret =3D smu_v11_0_get_dpm_freq_by_ind= ex(smu, SMU_VCLK, 0, &freq);
+       if (ret)
+            &n= bsp;  goto out;
+       gpu_metrics->min_vclk0_frequency = =3D freq;
+
+       ret =3D smu_v11_0_get_dpm_freq_by_ind= ex(smu, SMU_DCLK, 0, &freq);
+       if (ret)
+            &n= bsp;  goto out;
+       gpu_metrics->min_dclk0_frequency = =3D freq;
+
+       ret =3D smu_v11_0_get_dpm_level_count= (smu, SMU_GFXCLK, &dpm);
+       if (ret)
+            &n= bsp;  goto out;
+       gpu_metrics->max_gfxclk_dpm =3D dp= m;
+
+       ret =3D smu_v11_0_get_dpm_freq_by_ind= ex(smu, SMU_GFXCLK,
+            &n= bsp;          gpu_metrics->= max_gfxclk_dpm - 1, &freq);
+       if (ret)
+            &n= bsp;  goto out;
+
+       gpu_metrics->max_gfxclk_frequency = =3D freq;
+
+       ret =3D smu_v11_0_get_dpm_level_count= (smu, SMU_SOCCLK, &dpm);
+       if (ret)
+            &n= bsp;  goto out;
+
+       gpu_metrics->max_socclk_dpm =3D dp= m;
+
+       ret =3D smu_v11_0_get_dpm_freq_by_ind= ex(smu, SMU_SOCCLK,
+            &n= bsp;          gpu_metrics->= max_socclk_dpm - 1, &freq);
+       if (ret)
+            &n= bsp;  goto out;
+
+       gpu_metrics->max_socclk_frequency = =3D freq;
+
+       ret =3D smu_v11_0_get_dpm_level_count= (smu, SMU_UCLK, &dpm);
+       if (ret)
+            &n= bsp;  goto out;
+
+       gpu_metrics->max_uclk_dpm =3D dpm;=
+
+       ret =3D smu_v11_0_get_dpm_freq_by_ind= ex(smu, SMU_UCLK,
+            &n= bsp;          gpu_metrics->= max_uclk_dpm - 1, &freq);
+       if (ret)
+            &n= bsp;  goto out;
+
+       gpu_metrics->max_uclk_frequency = =3D freq;
+
+       ret =3D smu_v11_0_get_dpm_level_count= (smu, SMU_VCLK, &dpm);
+       if (ret)
+            &n= bsp;  goto out;
+
+       gpu_metrics->max_vclk0_dpm =3D dpm= ;
+
+       ret =3D smu_v11_0_get_dpm_freq_by_ind= ex(smu, SMU_VCLK,
+            &n= bsp;          gpu_metrics->= max_vclk0_dpm - 1, &freq);
+       if (ret)
+            &n= bsp;  goto out;
+
+       gpu_metrics->max_vclk0_frequency = =3D freq;
+
+       ret =3D smu_v11_0_get_dpm_level_count= (smu, SMU_DCLK, &dpm);
+       if (ret)
+            &n= bsp;  goto out;
+
+       gpu_metrics->max_dclk0_dpm =3D dpm= ;
+
+       ret =3D smu_v11_0_get_dpm_freq_by_ind= ex(smu, SMU_DCLK,
+            &n= bsp;          gpu_metrics->= max_dclk0_dpm - 1, &freq);
+       if (ret)
+            &n= bsp;  goto out;
+
+       gpu_metrics->max_dclk0_frequency = =3D freq;
+
         *table =3D (void *)gpu_met= rics;
 
-       return sizeof(struct gpu_metrics_v1_1= );
+       return sizeof(struct gpu_metrics_v1_3= );
+out:
+       return ret;
 }
 
 static ssize_t navi12_get_legacy_gpu_metrics(struct smu_context *smu,=
            &nb= sp;            =             &nb= sp;        void **table)
 {
         struct smu_table_context *= smu_table =3D &smu->smu_table;
-       struct gpu_metrics_v1_1 *gpu_metrics = =3D
-            &n= bsp;  (struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table;
+       struct gpu_metrics_v1_3 *gpu_metrics = =3D
+            &n= bsp;  (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
         SmuMetrics_NV12_legacy_t m= etrics;
         int ret =3D 0;
+       int freq =3D 0, dpm =3D 0;
 
         mutex_lock(&smu->me= trics_lock);
 
@@ -2774,7 +2975,7 @@ static ssize_t navi12_get_legacy_gpu_metrics(struct s= mu_context *smu,
 
         mutex_unlock(&smu->= metrics_lock);
 
-       smu_cmn_init_soft_gpu_metrics(gpu_met= rics, 1, 1);
+       smu_cmn_init_soft_gpu_metrics(gpu_met= rics, 1, 3);
 
         gpu_metrics->temperatur= e_edge =3D metrics.TemperatureEdge;
         gpu_metrics->temperatur= e_hotspot =3D metrics.TemperatureHotspot; @@ -2814,19 +3015,119 @@ static s= size_t navi12_get_legacy_gpu_metrics(struct smu_context *smu,
 
         gpu_metrics->system_clo= ck_counter =3D ktime_get_boottime_ns();
 
+       gpu_metrics->voltage_gfx =3D (1550= 00 - 625 * metrics.CurrGfxVoltageOffset) / 100;
+       gpu_metrics->voltage_mem =3D (1550= 00 - 625 * metrics.CurrMemVidOffset) / 100;
+       gpu_metrics->voltage_soc =3D (1550= 00 - 625 *
+metrics.CurrSocVoltageOffset) / 100;
+
+       gpu_metrics->max_socket_power =3D = smu->power_limit;
+
+       /* Frequency and DPM ranges */
+
+       ret =3D smu_v11_0_get_dpm_freq_by_ind= ex(smu, SMU_GFXCLK, 0, &freq);
+       if (ret)
+            &n= bsp;  goto out;
+       gpu_metrics->min_gfxclk_frequency = =3D freq;
+
+       ret =3D smu_v11_0_get_dpm_freq_by_ind= ex(smu, SMU_SOCCLK, 0, &freq);
+       if (ret)
+            &n= bsp;  goto out;
+       gpu_metrics->min_socclk_frequency = =3D freq;
+
+       ret =3D smu_v11_0_get_dpm_freq_by_ind= ex(smu, SMU_UCLK, 0, &freq);
+       if (ret)
+            &n= bsp;  goto out;
+       gpu_metrics->min_uclk_frequency = =3D freq;
+
+       ret =3D smu_v11_0_get_dpm_freq_by_ind= ex(smu, SMU_VCLK, 0, &freq);
+       if (ret)
+            &n= bsp;  goto out;
+       gpu_metrics->min_vclk0_frequency = =3D freq;
+
+       ret =3D smu_v11_0_get_dpm_freq_by_ind= ex(smu, SMU_DCLK, 0, &freq);
+       if (ret)
+            &n= bsp;  goto out;
+       gpu_metrics->min_dclk0_frequency = =3D freq;
+
+       ret =3D smu_v11_0_get_dpm_level_count= (smu, SMU_GFXCLK, &dpm);
+       if (ret)
+            &n= bsp;  goto out;
+       gpu_metrics->max_gfxclk_dpm =3D dp= m;
+
+       ret =3D smu_v11_0_get_dpm_freq_by_ind= ex(smu, SMU_GFXCLK,
+            &n= bsp;          gpu_metrics->= max_gfxclk_dpm - 1, &freq);
+       if (ret)
+            &n= bsp;  goto out;
+
+       gpu_metrics->max_gfxclk_frequency = =3D freq;
+
+       ret =3D smu_v11_0_get_dpm_level_count= (smu, SMU_SOCCLK, &dpm);
+       if (ret)
+            &n= bsp;  goto out;
+
+       gpu_metrics->max_socclk_dpm =3D dp= m;
+
+       ret =3D smu_v11_0_get_dpm_freq_by_ind= ex(smu, SMU_SOCCLK,
+            &n= bsp;          gpu_metrics->= max_socclk_dpm - 1, &freq);
+       if (ret)
+            &n= bsp;  goto out;
+
+       gpu_metrics->max_socclk_frequency = =3D freq;
+
+       ret =3D smu_v11_0_get_dpm_level_count= (smu, SMU_UCLK, &dpm);
+       if (ret)
+            &n= bsp;  goto out;
+
+       gpu_metrics->max_uclk_dpm =3D dpm;=
+
+       ret =3D smu_v11_0_get_dpm_freq_by_ind= ex(smu, SMU_UCLK,
+            &n= bsp;          gpu_metrics->= max_uclk_dpm - 1, &freq);
+       if (ret)
+            &n= bsp;  goto out;
+
+       gpu_metrics->max_uclk_frequency = =3D freq;
+
+       ret =3D smu_v11_0_get_dpm_level_count= (smu, SMU_VCLK, &dpm);
+       if (ret)
+            &n= bsp;  goto out;
+
+       gpu_metrics->max_vclk0_dpm =3D dpm= ;
+
+       ret =3D smu_v11_0_get_dpm_freq_by_ind= ex(smu, SMU_VCLK,
+            &n= bsp;          gpu_metrics->= max_vclk0_dpm - 1, &freq);
+       if (ret)
+            &n= bsp;  goto out;
+
+       gpu_metrics->max_vclk0_frequency = =3D freq;
+
+       ret =3D smu_v11_0_get_dpm_level_count= (smu, SMU_DCLK, &dpm);
+       if (ret)
+            &n= bsp;  goto out;
+
+       gpu_metrics->max_dclk0_dpm =3D dpm= ;
+
+       ret =3D smu_v11_0_get_dpm_freq_by_ind= ex(smu, SMU_DCLK,
+            &n= bsp;          gpu_metrics->= max_dclk0_dpm - 1, &freq);
+       if (ret)
+            &n= bsp;  goto out;
+
+       gpu_metrics->max_dclk0_frequency = =3D freq;
+
         *table =3D (void *)gpu_met= rics;
 
-       return sizeof(struct gpu_metrics_v1_1= );
+       return sizeof(struct gpu_metrics_v1_3= );
+out:
+       return ret;
 }
 
 static ssize_t navi12_get_gpu_metrics(struct smu_context *smu,
            &nb= sp;            =             &nb= sp; void **table)
 {
         struct smu_table_context *= smu_table =3D &smu->smu_table;
-       struct gpu_metrics_v1_1 *gpu_metrics = =3D
-            &n= bsp;  (struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table;
+       struct gpu_metrics_v1_3 *gpu_metrics = =3D
+            &n= bsp;  (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
         SmuMetrics_NV12_t metrics;=
         int ret =3D 0;
+       int freq =3D 0, dpm =3D 0;
 
         mutex_lock(&smu->me= trics_lock);
 
@@ -2842,7 +3143,7 @@ static ssize_t navi12_get_gpu_metrics(struct smu_cont= ext *smu,
 
         mutex_unlock(&smu->= metrics_lock);
 
-       smu_cmn_init_soft_gpu_metrics(gpu_met= rics, 1, 1);
+       smu_cmn_init_soft_gpu_metrics(gpu_met= rics, 1, 3);
 
         gpu_metrics->temperatur= e_edge =3D metrics.TemperatureEdge;
         gpu_metrics->temperatur= e_hotspot =3D metrics.TemperatureHotspot; @@ -2884,9 +3185,108 @@ static ss= ize_t navi12_get_gpu_metrics(struct smu_context *smu,
 
         gpu_metrics->system_clo= ck_counter =3D ktime_get_boottime_ns();
 
+       gpu_metrics->voltage_gfx =3D (1550= 00 - 625 * metrics.CurrGfxVoltageOffset) / 100;
+       gpu_metrics->voltage_mem =3D (1550= 00 - 625 * metrics.CurrMemVidOffset) / 100;
+       gpu_metrics->voltage_soc =3D (1550= 00 - 625 *
+metrics.CurrSocVoltageOffset) / 100;
+
+       gpu_metrics->max_socket_power =3D = smu->power_limit;
+
+       /* Frequency and DPM ranges */
+
+       ret =3D smu_v11_0_get_dpm_freq_by_ind= ex(smu, SMU_GFXCLK, 0, &freq);
+       if (ret)
+            &n= bsp;  goto out;
+       gpu_metrics->min_gfxclk_frequency = =3D freq;
+
+       ret =3D smu_v11_0_get_dpm_freq_by_ind= ex(smu, SMU_SOCCLK, 0, &freq);
+       if (ret)
+            &n= bsp;  goto out;
+       gpu_metrics->min_socclk_frequency = =3D freq;
+
+       ret =3D smu_v11_0_get_dpm_freq_by_ind= ex(smu, SMU_UCLK, 0, &freq);
+       if (ret)
+            &n= bsp;  goto out;
+       gpu_metrics->min_uclk_frequency = =3D freq;
+
+       ret =3D smu_v11_0_get_dpm_freq_by_ind= ex(smu, SMU_VCLK, 0, &freq);
+       if (ret)
+            &n= bsp;  goto out;
+       gpu_metrics->min_vclk0_frequency = =3D freq;
+
+       ret =3D smu_v11_0_get_dpm_freq_by_ind= ex(smu, SMU_DCLK, 0, &freq);
+       if (ret)
+            &n= bsp;  goto out;
+       gpu_metrics->min_dclk0_frequency = =3D freq;
+
+       ret =3D smu_v11_0_get_dpm_level_count= (smu, SMU_GFXCLK, &dpm);
+       if (ret)
+            &n= bsp;  goto out;
+       gpu_metrics->max_gfxclk_dpm =3D dp= m;
+
+       ret =3D smu_v11_0_get_dpm_freq_by_ind= ex(smu, SMU_GFXCLK,
+            &n= bsp;          gpu_metrics->= max_gfxclk_dpm - 1, &freq);
+       if (ret)
+            &n= bsp;  goto out;
+
+       gpu_metrics->max_gfxclk_frequency = =3D freq;
+
+       ret =3D smu_v11_0_get_dpm_level_count= (smu, SMU_SOCCLK, &dpm);
+       if (ret)
+            &n= bsp;  goto out;
+
+       gpu_metrics->max_socclk_dpm =3D dp= m;
+
+       ret =3D smu_v11_0_get_dpm_freq_by_ind= ex(smu, SMU_SOCCLK,
+            &n= bsp;          gpu_metrics->= max_socclk_dpm - 1, &freq);
+       if (ret)
+            &n= bsp;  goto out;
+
+       gpu_metrics->max_socclk_frequency = =3D freq;
+
+       ret =3D smu_v11_0_get_dpm_level_count= (smu, SMU_UCLK, &dpm);
+       if (ret)
+            &n= bsp;  goto out;
+
+       gpu_metrics->max_uclk_dpm =3D dpm;=
+
+       ret =3D smu_v11_0_get_dpm_freq_by_ind= ex(smu, SMU_UCLK,
+            &n= bsp;          gpu_metrics->= max_uclk_dpm - 1, &freq);
+       if (ret)
+            &n= bsp;  goto out;
+
+       gpu_metrics->max_uclk_frequency = =3D freq;
+
+       ret =3D smu_v11_0_get_dpm_level_count= (smu, SMU_VCLK, &dpm);
+       if (ret)
+            &n= bsp;  goto out;
+
+       gpu_metrics->max_vclk0_dpm =3D dpm= ;
+
+       ret =3D smu_v11_0_get_dpm_freq_by_ind= ex(smu, SMU_VCLK,
+            &n= bsp;          gpu_metrics->= max_vclk0_dpm - 1, &freq);
+       if (ret)
+            &n= bsp;  goto out;
+
+       gpu_metrics->max_vclk0_frequency = =3D freq;
+
+       ret =3D smu_v11_0_get_dpm_level_count= (smu, SMU_DCLK, &dpm);
+       if (ret)
+            &n= bsp;  goto out;
+
+       gpu_metrics->max_dclk0_dpm =3D dpm= ;
+
+       ret =3D smu_v11_0_get_dpm_freq_by_ind= ex(smu, SMU_DCLK,
+            &n= bsp;          gpu_metrics->= max_dclk0_dpm - 1, &freq);
+       if (ret)
+            &n= bsp;  goto out;
+
+       gpu_metrics->max_dclk0_frequency = =3D freq;
+
         *table =3D (void *)gpu_met= rics;
 
-       return sizeof(struct gpu_metrics_v1_1= );
+       return sizeof(struct gpu_metrics_v1_3= );
+out:
+       return ret;
 }
 
 static ssize_t navi1x_get_gpu_metrics(struct smu_context *smu,
--
2.17.1

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