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boundary="===============0180434193==" Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" --===============0180434193== Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_BYAPR12MB32222491A1C7877B86C69B43E1CD0BYAPR12MB3222namp_" --_000_BYAPR12MB32222491A1C7877B86C69B43E1CD0BYAPR12MB3222namp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable [AMD Public Use] Hi Hawking, The process is to send request first, and then to poll and wait 6 seconds. So the time delta between the 1-st request and the 11-th request is actuall= y 60 seconds. Jiange ________________________________ From: Zhang, Hawking Sent: Tuesday, December 8, 2020 12:16 AM To: Zhao, Jiange ; amd-gfx@lists.freedesktop.org Cc: Chen, Horace ; Zhang, Andy Subject: RE: [PATCH] drm/amdgpu/SRIOV: Extend VF reset request wait period [AMD Public Use] Re - Poll happens every 6 seconds and it will last for 60 seconds. + int ret, i =3D 0; + #define AI_MAILBOX_POLL_MSG_REP_MAX 11 The definition seems not match with your description that the polling will = last for 60s.... with that fixed, the patch is Acked-by: Hawking Zhang Regards, Hawking -----Original Message----- From: Zhao, Jiange Sent: Monday, December 7, 2020 18:06 To: amd-gfx@lists.freedesktop.org Cc: Zhang, Hawking ; Chen, Horace ; Zhang, Andy ; Zhao, Jiange Subject: [PATCH] drm/amdgpu/SRIOV: Extend VF reset request wait period From: Jiange Zhao In Virtualization case, when one VF is sending too many FLR requests, hyper= visor would stop responding to this VF's request for a long period of time.= This is called event guard. During this period of cooling time, guest driv= er should wait instead of doing other things. After this period of time, gu= est driver would resume reset process and return to normal. Currently, guest driver would wait 12 seconds and return fail if it doesn't= get response from host. Solution: extend this waiting time in guest driver and poll response period= ically. Poll happens every 6 seconds and it will last for 60 seconds. v2: change the max repetition times from number to macro. Signed-off-by: Jiange Zhao --- drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | 11 ++++++++++- drivers/gpu/drm/am= d/amdgpu/mxgpu_ai.h | 3 ++- drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c | 11 ++= ++++++++- drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h | 1 + 4 files changed, 23 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c b/drivers/gpu/drm/amd/am= dgpu/mxgpu_ai.c index f5ce9a9f4cf5..7767ccca526b 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c @@ -187,7 +187,16 @@ static int xgpu_ai_send_access_requests(struct amdgpu_= device *adev, static int xgpu_ai_request_reset(struct amdgpu_device *adev) { - return xgpu_ai_send_access_requests(adev, IDH_REQ_GPU_RESET_ACCESS)= ; + int ret, i =3D 0; + + while (i < AI_MAILBOX_POLL_MSG_REP_MAX) { + ret =3D xgpu_ai_send_access_requests(adev, IDH_REQ_GPU_RESE= T_ACCESS); + if (!ret) + break; + i++; + } + + return ret; } static int xgpu_ai_request_full_gpu_access(struct amdgpu_device *adev, dif= f --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h b/drivers/gpu/drm/amd/amdgp= u/mxgpu_ai.h index 83b453f5d717..50572635d0f8 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h @@ -25,8 +25,9 @@ #define __MXGPU_AI_H__ #define AI_MAILBOX_POLL_ACK_TIMEDOUT 500 -#define AI_MAILBOX_POLL_MSG_TIMEDOUT 12000 +#define AI_MAILBOX_POLL_MSG_TIMEDOUT 6000 #define AI_MAILBOX_POLL_FLR_TIMEDOUT 5000 +#define AI_MAILBOX_POLL_MSG_REP_MAX 11 enum idh_request { IDH_REQ_GPU_INIT_ACCESS =3D 1, diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c b/drivers/gpu/drm/amd/am= dgpu/mxgpu_nv.c index 666ed99cc14b..dd5c1e6ce009 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c @@ -200,7 +200,16 @@ static int xgpu_nv_send_access_requests(struct amdgpu_= device *adev, static int xgpu_nv_request_reset(struct amdgpu_device *adev) { - return xgpu_nv_send_access_requests(adev, IDH_REQ_GPU_RESET_ACCESS)= ; + int ret, i =3D 0; + + while (i < NV_MAILBOX_POLL_MSG_REP_MAX) { + ret =3D xgpu_nv_send_access_requests(adev, IDH_REQ_GPU_RESE= T_ACCESS); + if (!ret) + break; + i++; + } + + return ret; } static int xgpu_nv_request_full_gpu_access(struct amdgpu_device *adev, dif= f --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h b/drivers/gpu/drm/amd/amdgp= u/mxgpu_nv.h index 52605e14a1a5..9f5808616174 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h @@ -27,6 +27,7 @@ #define NV_MAILBOX_POLL_ACK_TIMEDOUT 500 #define NV_MAILBOX_POLL_MSG_TIMEDOUT 6000 #define NV_MAILBOX_POLL_FLR_TIMEDOUT 5000 +#define NV_MAILBOX_POLL_MSG_REP_MAX 11 enum idh_request { IDH_REQ_GPU_INIT_ACCESS =3D 1, -- 2.25.1 --_000_BYAPR12MB32222491A1C7877B86C69B43E1CD0BYAPR12MB3222namp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

[AMD Public Use]


Hi Hawking,

The process is to send request first, and then to poll and wait 6 seconds.<= /div>

So the time delta between the 1-st request and the 11-th request is actuall= y 60 seconds.

Jiange
From: Zhang, Hawking <Ha= wking.Zhang@amd.com>
Sent: Tuesday, December 8, 2020 12:16 AM
To: Zhao, Jiange <Jiange.Zhao@amd.com>; amd-gfx@lists.freedesk= top.org <amd-gfx@lists.freedesktop.org>
Cc: Chen, Horace <Horace.Chen@amd.com>; Zhang, Andy <Andy.Z= hang@amd.com>
Subject: RE: [PATCH] drm/amdgpu/SRIOV: Extend VF reset request wait = period
 
[AMD Public Use]

Re - Poll happens every 6 seconds and it will last for 60 seconds.
+       int ret, i =3D 0;
+       #define AI_MAILBOX_POLL_MSG_REP_MAX&n= bsp;    11

The definition seems not match with your description that the polling will = last for 60s.... with that fixed, the patch is

Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>

Regards,
Hawking
-----Original Message-----
From: Zhao, Jiange <Jiange.Zhao@amd.com>
Sent: Monday, December 7, 2020 18:06
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking <Hawking.Zhang@amd.com>; Chen, Horace <Horace.C= hen@amd.com>; Zhang, Andy <Andy.Zhang@amd.com>; Zhao, Jiange <J= iange.Zhao@amd.com>
Subject: [PATCH] drm/amdgpu/SRIOV: Extend VF reset request wait period

From: Jiange Zhao <Jiange.Zhao@amd.com>

In Virtualization case, when one VF is sending too many FLR requests, hyper= visor would stop responding to this VF's request for a long period of time.= This is called event guard. During this period of cooling time, guest driv= er should wait instead of doing other things. After this period of time, guest driver would resume reset p= rocess and return to normal.

Currently, guest driver would wait 12 seconds and return fail if it doesn't= get response from host.

Solution: extend this waiting time in guest driver and poll response period= ically. Poll happens every 6 seconds and it will last for 60 seconds.

v2: change the max repetition times from number to macro.

Signed-off-by: Jiange Zhao <Jiange.Zhao@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | 11 ++++++++++-  drivers/= gpu/drm/amd/amdgpu/mxgpu_ai.h |  3 ++-  drivers/gpu/drm/amd/amdgp= u/mxgpu_nv.c | 11 ++++++++++-  drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h |=   1 +
 4 files changed, 23 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c b/drivers/gpu/drm/amd/am= dgpu/mxgpu_ai.c
index f5ce9a9f4cf5..7767ccca526b 100644
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
@@ -187,7 +187,16 @@ static int xgpu_ai_send_access_requests(struct amdgpu_= device *adev,
 
 static int xgpu_ai_request_reset(struct amdgpu_device *adev)  {<= br> -       return xgpu_ai_send_access_requests(a= dev, IDH_REQ_GPU_RESET_ACCESS);
+       int ret, i =3D 0;
+
+       while (i < AI_MAILBOX_POLL_MSG_REP= _MAX) {
+            &n= bsp;  ret =3D xgpu_ai_send_access_requests(adev, IDH_REQ_GPU_RESET_ACC= ESS);
+            &n= bsp;  if (!ret)
+            &n= bsp;          break;
+            &n= bsp;  i++;
+       }
+
+       return ret;
 }
 
 static int xgpu_ai_request_full_gpu_access(struct amdgpu_device *adev= , diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h b/drivers/gpu/drm/amd/= amdgpu/mxgpu_ai.h
index 83b453f5d717..50572635d0f8 100644
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h
@@ -25,8 +25,9 @@
 #define __MXGPU_AI_H__
 
 #define AI_MAILBOX_POLL_ACK_TIMEDOUT    500
-#define AI_MAILBOX_POLL_MSG_TIMEDOUT   12000
+#define AI_MAILBOX_POLL_MSG_TIMEDOUT   6000
 #define AI_MAILBOX_POLL_FLR_TIMEDOUT    5000
+#define AI_MAILBOX_POLL_MSG_REP_MAX    11
 
 enum idh_request {
         IDH_REQ_GPU_INIT_ACCESS = =3D 1,
diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c b/drivers/gpu/drm/amd/am= dgpu/mxgpu_nv.c
index 666ed99cc14b..dd5c1e6ce009 100644
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c
@@ -200,7 +200,16 @@ static int xgpu_nv_send_access_requests(struct amdgpu_= device *adev,
 
 static int xgpu_nv_request_reset(struct amdgpu_device *adev)  {<= br> -       return xgpu_nv_send_access_requests(a= dev, IDH_REQ_GPU_RESET_ACCESS);
+       int ret, i =3D 0;
+
+       while (i < NV_MAILBOX_POLL_MSG_REP= _MAX) {
+            &n= bsp;  ret =3D xgpu_nv_send_access_requests(adev, IDH_REQ_GPU_RESET_ACC= ESS);
+            &n= bsp;  if (!ret)
+            &n= bsp;          break;
+            &n= bsp;  i++;
+       }
+
+       return ret;
 }
 
 static int xgpu_nv_request_full_gpu_access(struct amdgpu_device *adev= , diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h b/drivers/gpu/drm/amd/= amdgpu/mxgpu_nv.h
index 52605e14a1a5..9f5808616174 100644
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h
@@ -27,6 +27,7 @@
 #define NV_MAILBOX_POLL_ACK_TIMEDOUT    500
 #define NV_MAILBOX_POLL_MSG_TIMEDOUT    6000
 #define NV_MAILBOX_POLL_FLR_TIMEDOUT    5000
+#define NV_MAILBOX_POLL_MSG_REP_MAX    11
 
 enum idh_request {
         IDH_REQ_GPU_INIT_ACCESS = =3D 1,
--
2.25.1
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