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boundary="===============1306425047==" Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" --===============1306425047== Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_BYAPR12MB4759A953391A086672B58D43BB239BYAPR12MB4759namp_" --_000_BYAPR12MB4759A953391A086672B58D43BB239BYAPR12MB4759namp_ Content-Type: text/plain; charset="Windows-1252" Content-Transfer-Encoding: quoted-printable Hi, friends. My apologize for this patch. I=92ve ported this patch from another branch to fix gstreamer=92s lack of = =93vaapi264enc=94, currently this ported patch did fix that issue. However,= since this patch is ported from another branch, I might need to do some al= ternations and audits mainly in its commit messages. I will file another re= view right after my fixes. Thank you all for you time. BR, Justin From: Liu, Monk Date: Thursday, May 27, 2021 at 07:57 To: Li, Xin (Justin) , amd-gfx@lists.freedesktop.org Cc: Li, Xin (Justin) , Deucher, Alexander , Min, Frank , Koenig, Christian Subject: RE: [PATCH] drm/amdgpu: Fix Gstreamer api vaapih264enc missing [AMD Official Use Only] Looks it lack enough background for people to review: - if (adev->vcn.inst[i].ring_dec.sched.ready) + if (adev->vcn.inst[i].ring_dec.sched.ready || + (adev->asic_type =3D=3D CHIP_NAVI12 && + amdgpu_sriov_vf(adev))) ++num_rings; [ml] why for SRIOV navi12 is forced to have those DEC rings ? since SRIOV = navi12 have no decode capability , any explain here ? - if (amdgpu_is_tmz(adev)) - dev_info->ids_flags |=3D AMDGPU_IDS_FLAGS_TMZ; [ML] why this is removed ? is it related to your issue ? Thanks ------------------------------------------ Monk Liu | Cloud-GPU Core team ------------------------------------------ -----Original Message----- From: amd-gfx On Behalf Of Li, Xin = (Justin) Sent: Wednesday, May 26, 2021 6:13 PM To: amd-gfx@lists.freedesktop.org Cc: Li, Xin (Justin) ; Deucher, Alexander ; Min, Frank ; Koenig, Christian Subject: [PATCH] drm/amdgpu: Fix Gstreamer api vaapih264enc missing since vcn decoding ring is not required, so just disable it. Cc: Alex.Deucher Cc: Christian.Konig Signed-off-by: Li.Xin.Justin Signed-off-by: Frank.Min --- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 25 ++++++++++++++----------- 2 files changed, 17 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_kms.c index 524e4fe5efe8..614e6b06e94e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -427,7 +427,9 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev= , if (adev->uvd.harvest_config & (1 << i)) continue; - if (adev->vcn.inst[i].ring_dec.sched.ready) + if (adev->vcn.inst[i].ring_dec.sched.ready || + (adev->asic_type =3D=3D CHIP_NAVI12 && + amdgpu_sriov_vf(adev))) ++num_rings; } ib_start_alignment =3D 16; @@ -770,8 +772,6 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *dat= a, struct drm_file *filp) dev_info->ids_flags |=3D AMDGPU_IDS_FLAGS_FUSION; if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) dev_info->ids_flags |=3D AMDGPU_IDS_FLAGS_PREEMPTI= ON; - if (amdgpu_is_tmz(adev)) - dev_info->ids_flags |=3D AMDGPU_IDS_FLAGS_TMZ; vm_size =3D adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZ= E; vm_size -=3D AMDGPU_VA_RESERVED_SIZE; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/am= dgpu/vcn_v2_0.c index 8af567c546db..dc8a36766c4a 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c @@ -220,17 +220,20 @@ static int vcn_v2_0_hw_init(void *handle) { struct amdgpu_device *adev =3D (struct amdgpu_device *)handle; struct amdgpu_ring *ring =3D &adev->vcn.inst->ring_dec; - int i, r; + int i, r =3D -1; adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, ring->doorbell_index, 0); - if (amdgpu_sriov_vf(adev)) + if (amdgpu_sriov_vf(adev)) { vcn_v2_0_start_sriov(adev); - - r =3D amdgpu_ring_test_helper(ring); - if (r) - goto done; + if (adev->asic_type =3D=3D CHIP_NAVI12) + ring->sched.ready =3D false; + } else { + r =3D amdgpu_ring_test_helper(ring); + if (r) + goto done; + } //Disable vcn decode for sriov if (amdgpu_sriov_vf(adev)) @@ -245,8 +248,11 @@ static int vcn_v2_0_hw_init(void *handle) done: if (!r) - DRM_INFO("VCN decode and encode initialized successfully(un= der %s).\n", - (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode= ":"SPG Mode"); + DRM_INFO("VCN %s encode initialized successfully(under %s).= \n", + (adev->asic_type =3D=3D CHIP_NAVI12 && + amdgpu_sriov_vf(adev))?"":"decode and", + (adev->pg_flags & + AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mod= e"); return r; } @@ -1721,9 +1727,6 @@ int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring *r= ing) unsigned i; int r; - if (amdgpu_sriov_vf(adev)) - return 0; - WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD); r =3D amdgpu_ring_alloc(ring, 4); if (r) -- 2.25.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2Flists.f= reedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=3D04%7C01%7Cmonk.liu= %40amd.com%7Cb86e27d9b55f429b352308d9202ee408%7C3dd8961fe4884e608e11a82d994= e183d%7C0%7C0%7C637576208056272141%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAw= MDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=3DcMllN= 28FN56voTpWwdnMmBB3CGXezs%2FaEwflSZD6qr4%3D&reserved=3D0 --_000_BYAPR12MB4759A953391A086672B58D43BB239BYAPR12MB4759namp_ Content-Type: text/html; charset="Windows-1252" Content-Transfer-Encoding: quoted-printable

Hi, friends.

 

My apologize for this patch.

 

I=92ve ported this patch from another branch to fix = gstreamer=92s lack of =93vaapi264enc=94, currently this ported patch did fi= x that issue. However, since this patch is ported from another branch, I mi= ght need to do some alternations and audits mainly in its commit messages. I will file another review right after my f= ixes.

 

Thank you all for you time.

 

BR,

Justin

 

From: Liu, Monk <Monk.= Liu@amd.com>
Date: Thursday, May 27, 2021 at 07:57
To: Li, Xin (Justin) <Xin2.Li@amd.com>, amd-gfx@lists.freedesk= top.org <amd-gfx@lists.freedesktop.org>
Cc: Li, Xin (Justin) <Xin2.Li@amd.com>, Deucher, Alexander <= ;Alexander.Deucher@amd.com>, Min, Frank <Frank.Min@amd.com>, Koeni= g, Christian <Christian.Koenig@amd.com>
Subject: RE: [PATCH] drm/amdgpu: Fix Gstreamer api vaapih264enc miss= ing

[AMD Official Use Only]

Looks it lack enough background for people to review:


-            &n= bsp;          if (adev->vcn= .inst[i].ring_dec.sched.ready)
+            &n= bsp;          if (adev->vcn= .inst[i].ring_dec.sched.ready ||
+            &n= bsp;            = ;      (adev->asic_type =3D=3D CHIP_NAVI12 &= ;&
+            &n= bsp;            = ;      amdgpu_sriov_vf(adev)))
            &nb= sp;            =         ++num_rings;

[ml] why for SRIOV navi12 is forced to have those DEC rings ? since  S= RIOV navi12 have no decode capability , any explain here ?


-            &n= bsp;  if (amdgpu_is_tmz(adev))
-            &n= bsp;          dev_info->ids= _flags |=3D AMDGPU_IDS_FLAGS_TMZ;
[ML] why this is removed ? is it related to your issue ?


Thanks

------------------------------------------
Monk Liu | Cloud-GPU Core team
------------------------------------------

-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Li= , Xin (Justin)
Sent: Wednesday, May 26, 2021 6:13 PM
To: amd-gfx@lists.freedesktop.org
Cc: Li, Xin (Justin) <Xin2.Li@amd.com>; Deucher, Alexander <Alexan= der.Deucher@amd.com>; Min, Frank <Frank.Min@amd.com>; Koenig, Chri= stian <Christian.Koenig@amd.com>
Subject: [PATCH] drm/amdgpu: Fix Gstreamer api vaapih264enc missing

since vcn decoding ring is not required, so just disable it.

Cc: Alex.Deucher <alexander.deucher@amd.com>
Cc: Christian.Konig <christian.koenig@amd.com>
Signed-off-by: Li.Xin.Justin <xin2.li@amd.com>
Signed-off-by: Frank.Min <Frank.Min@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c |  6 +++---
 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c   | 25 ++++++++++++++= -----------
 2 files changed, 17 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_kms.c
index 524e4fe5efe8..614e6b06e94e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -427,7 +427,9 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev= ,
            &nb= sp;            if (a= dev->uvd.harvest_config & (1 << i))
            &nb= sp;            =         continue;
 
-            &n= bsp;          if (adev->vcn= .inst[i].ring_dec.sched.ready)
+            &n= bsp;          if (adev->vcn= .inst[i].ring_dec.sched.ready ||
+            &n= bsp;            = ;      (adev->asic_type =3D=3D CHIP_NAVI12 &= ;&
+            &n= bsp;            = ;      amdgpu_sriov_vf(adev)))
            &nb= sp;            =         ++num_rings;
            &nb= sp;    }
            &nb= sp;    ib_start_alignment =3D 16;
@@ -770,8 +772,6 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *dat= a, struct drm_file *filp)
            &nb= sp;            dev_i= nfo->ids_flags |=3D AMDGPU_IDS_FLAGS_FUSION;
            &nb= sp;    if (amdgpu_mcbp || amdgpu_sriov_vf(adev))
            &nb= sp;            dev_i= nfo->ids_flags |=3D AMDGPU_IDS_FLAGS_PREEMPTION;
-            &n= bsp;  if (amdgpu_is_tmz(adev))
-            &n= bsp;          dev_info->ids= _flags |=3D AMDGPU_IDS_FLAGS_TMZ;
 
            &nb= sp;    vm_size =3D adev->vm_manager.max_pfn * AMDGPU_GPU_= PAGE_SIZE;
            &nb= sp;    vm_size -=3D AMDGPU_VA_RESERVED_SIZE;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/am= dgpu/vcn_v2_0.c
index 8af567c546db..dc8a36766c4a 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -220,17 +220,20 @@ static int vcn_v2_0_hw_init(void *handle)
 {
         struct amdgpu_device *adev= =3D (struct amdgpu_device *)handle;
         struct amdgpu_ring *ring = =3D &adev->vcn.inst->ring_dec;
-       int i, r;
+       int i, r =3D -1;
 
         adev->nbio.funcs->vc= n_doorbell_range(adev, ring->use_doorbell,
            &nb= sp;            =             &nb= sp;        ring->doorbell_index, 0);<= br>  
-       if (amdgpu_sriov_vf(adev))
+       if (amdgpu_sriov_vf(adev)) {
            &nb= sp;    vcn_v2_0_start_sriov(adev);
-
-       r =3D amdgpu_ring_test_helper(ring);<= br> -       if (r)
-            &n= bsp;  goto done;
+            &n= bsp;  if (adev->asic_type =3D=3D CHIP_NAVI12)
+            &n= bsp;          ring->sched.r= eady =3D false;
+       } else {
+            &n= bsp;  r =3D amdgpu_ring_test_helper(ring);
+            &n= bsp;  if (r)
+            &n= bsp;          goto done;
+       }
 
         //Disable vcn decode for s= riov
         if (amdgpu_sriov_vf(adev))=
@@ -245,8 +248,11 @@ static int vcn_v2_0_hw_init(void *handle)
 
 done:
         if (!r)
-            &n= bsp;  DRM_INFO("VCN decode and encode initialized successfully(un= der %s).\n",
-            &n= bsp;          (adev->pg_fla= gs & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode")= ;
+            &n= bsp;  DRM_INFO("VCN %s encode initialized successfully(under %s).= \n",
+            &n= bsp;          (adev->asic_t= ype =3D=3D CHIP_NAVI12 &&
+            &n= bsp;            = ;      amdgpu_sriov_vf(adev))?"":"d= ecode and",
+            &n= bsp;          (adev->pg_fla= gs &
+            &n= bsp;            = ;      AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode"= ;:"SPG Mode");
 
         return r;
 }
@@ -1721,9 +1727,6 @@ int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring *r= ing)
         unsigned i;
         int r;
 
-       if (amdgpu_sriov_vf(adev))
-            &n= bsp;  return 0;
-
         WREG32(adev->vcn.inst[r= ing->me].external.scratch9, 0xCAFEDEAD);
         r =3D amdgpu_ring_alloc(ri= ng, 4);
         if (r)
--
2.25.1

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