From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.6 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00387C433FF for ; Fri, 2 Aug 2019 11:20:03 +0000 (UTC) Received: from dpdk.org (dpdk.org [92.243.14.124]) by mail.kernel.org (Postfix) with ESMTP id 53A3420665 for ; Fri, 2 Aug 2019 11:20:03 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="rkjy1bDh"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=marvell.onmicrosoft.com header.i=@marvell.onmicrosoft.com header.b="a/1Kqmua" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 53A3420665 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=marvell.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=dev-bounces@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 4DD161C24E; Fri, 2 Aug 2019 13:20:02 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id DCA071C243 for ; Fri, 2 Aug 2019 13:20:00 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x72AeDZu025938; Fri, 2 Aug 2019 03:41:03 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : references : in-reply-to : content-type : content-transfer-encoding : mime-version; s=pfpt0818; bh=gm4Gga3/FQf/jhgOJzzOFLFSVsjLA1v/TnFWGmw6mSg=; b=rkjy1bDhmI4k8NKuvooczZ0iuvIany26JGl8MqZEjqhKxZBWW6KqwcOELIkA8MUJd0LM 4CJf47frGVsOAdXPvk6VE1edSYI2bDl6X1H+KZ5YoNwsdmvarRE2WQNY3lPFOz4Xylhf Tb+Sh7eQaDG/3A78biZ/pA3hp0sYgvuGkvyMOvLxM5UAvhIBPBDevMgPQfhK7QnbknNk WG/4G/V/wEMgXqzrUXDRetI+M1iL/VAa8tL+KZdwrstq2YjKRCmI87rvnitDnkovMcsl jIFmjHNxXlMCxEhhOIHtkucCaorN9xw88DkOoJAH45yYElFD5dWJWGr7oDJhESle38OC Ow== Received: from sc-exch04.marvell.com ([199.233.58.184]) by mx0a-0016f401.pphosted.com with ESMTP id 2u3jujqrf9-3 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Fri, 02 Aug 2019 03:41:03 -0700 Received: from SC-EXCH02.marvell.com (10.93.176.82) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Fri, 2 Aug 2019 03:41:03 -0700 Received: from NAM05-BY2-obe.outbound.protection.outlook.com (104.47.50.59) by SC-EXCH02.marvell.com (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1367.3 via Frontend Transport; Fri, 2 Aug 2019 03:41:02 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=FDq10YUbkeYZ1LFqSn1eO0/cIWlTop/eP6B7ACq2NxL0n7OuixPMfhCAR/J2gUBR6VCq2Fa0tlLnnx7zJQhvp9haAayFekCMif+gFXHF8VTIDnYTQxWN26TIPYJyUQXo2VeOstsNBHMOdGXJrg5v/CfySfLKmbBvCTnMpQWWu0NrpxWWwNXqv2+/Tm+HTBuuVwhPEIpiv0f9sjzJhTNPmsqkso+Ecr1/68811/RAcm+OPE79oE7AR0pDBMT1muP9QtDC6C8H98rNsdjsTWXjWWs0IYIt3TuT+PD8GrOUOu63zvzPlTCqZO/qCX4z8KXVyYekYU5FTZHNDpjPvt/KZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=gm4Gga3/FQf/jhgOJzzOFLFSVsjLA1v/TnFWGmw6mSg=; b=nJ6ZPrXW+aeJHSTjTCbgWDpvyBM0LfkFqUHEOfsvu35Z9xQ0DEupk8UkR7dCneTR0IkNkrmfvYHF0SqfMRyK8qglHTlvDrW1G2mKhDdkd81/MrHiAp1TdWXLQTDX8jFRpWwk/TKfxSjGQ2vfkIbsfswsgLuA0L57i5LRKhgBoCF7a/n00qVo5tC28NojJidCh0t6hYw7eG79uQAWGsztGFbWb1WitPU45aPVg7fvNGs8Jg6jvWuS7ZX9hyb9hCF417b/BBCGGX9mOyYbl0i5JCK14xeLDKzraCKeuhySX315vIpojyNsOqPNI9LI0MVCba4XQxLUOPTowIT/qWnVgA== ARC-Authentication-Results: i=1; mx.microsoft.com 1;spf=pass smtp.mailfrom=marvell.com;dmarc=pass action=none header.from=marvell.com;dkim=pass header.d=marvell.com;arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.onmicrosoft.com; s=selector2-marvell-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=gm4Gga3/FQf/jhgOJzzOFLFSVsjLA1v/TnFWGmw6mSg=; b=a/1KqmuaZFPX4/olPE82tKLFxnkO2JrPIIc5n0f5KRXnmgsRdHjE/UvBFed11hI6T7pnEqkGo6XbJtI5cMn7XSdL8ljFIy4B90Ppkl6k4bdODjTm8v1vpOMljnH+TgbZEPfgLtlz0T2OVfrWlwKpn01/rk3UuM33CWeZxe0miCE= Received: from BYAPR18MB2424.namprd18.prod.outlook.com (20.179.91.149) by BYAPR18MB2520.namprd18.prod.outlook.com (20.179.93.12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2136.17; Fri, 2 Aug 2019 10:41:01 +0000 Received: from BYAPR18MB2424.namprd18.prod.outlook.com ([fe80::2d42:12b6:aa2e:2862]) by BYAPR18MB2424.namprd18.prod.outlook.com ([fe80::2d42:12b6:aa2e:2862%4]) with mapi id 15.20.2115.005; Fri, 2 Aug 2019 10:41:01 +0000 From: Jerin Jacob Kollanukkaran To: "Zhang, Tianfei" , "Xu, Rosen" , "dev@dpdk.org" CC: "Yigit, Ferruh" , "Pei, Andy" , "Lomartire, David" , "Zhang, Qi Z" , "Ye, Xiaolong" Thread-Topic: [dpdk-dev] [PATCH v2 02/12] raw/ifpga_rawdev/base: add irq support Thread-Index: AQHVSNAwWxMTLMsD0U6aTXPsnsjO+KbnOvfwgABnEwCAAAlnwA== Date: Fri, 2 Aug 2019 10:41:00 +0000 Message-ID: References: <1564556752-19257-2-git-send-email-rosen.xu@intel.com> <1564708727-164887-1-git-send-email-rosen.xu@intel.com> <1564708727-164887-3-git-send-email-rosen.xu@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [14.140.231.66] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: bb3348b9-bc69-4ca5-aee4-08d71735e943 x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(7168020)(4627221)(201703031133081)(201702281549075)(8990200)(5600148)(711020)(4605104)(1401327)(2017052603328)(7193020); SRVR:BYAPR18MB2520; x-ms-traffictypediagnostic: BYAPR18MB2520: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:7219; x-forefront-prvs: 011787B9DD x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(4636009)(396003)(136003)(366004)(376002)(346002)(39850400004)(189003)(199004)(13464003)(86362001)(25786009)(6506007)(53546011)(476003)(76116006)(14454004)(305945005)(7736002)(2501003)(68736007)(110136005)(4326008)(54906003)(6246003)(316002)(55236004)(102836004)(8936002)(74316002)(53936002)(71200400001)(9686003)(99286004)(52536014)(14444005)(71190400001)(6116002)(3846002)(186003)(6436002)(55016002)(5660300002)(66066001)(76176011)(11346002)(446003)(229853002)(478600001)(66476007)(33656002)(66446008)(64756008)(66556008)(2906002)(66946007)(7696005)(81156014)(26005)(256004)(8676002)(486006)(81166006); DIR:OUT; SFP:1101; SCL:1; SRVR:BYAPR18MB2520; H:BYAPR18MB2424.namprd18.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: marvell.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: 0MX1DARHo3TeK+S/4mJOwpqga+8VecSSnnxNBIsetPypby19G1I7ab/76n+FAqwa9g4jxHAjr8GagPPjX421jFic9Arvt1CsBRBFNUSLfhpCtH6vExsC7o54cYQ/+Dvl1xNnCzgMWlvZQYGJArL+fZTnnkZowEeTBc8/elrixFxusaox94yx55/n1yfi2lEozvN+yrph/EK4TH8dRULoKTyao0bHCmYGYp6yJdN2xnY6jH0l8WZChMxWLEeWo1UF2C7Cw3J+uEenPBDOro+P2NN4nYJJO1HM6css2Keo6QbTtpAs+5eAjGBRu1WLZ421Jxqc9aS9tUJ3bRYGGT0p2nXjVbEuMcYiWXVeigxoG2UOixkTX9bn+qMSc6/5wBbQgU4Bma1MDkR1CLPms5jBU2oHKtBUwB9PpveFWgeQluQ= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: bb3348b9-bc69-4ca5-aee4-08d71735e943 X-MS-Exchange-CrossTenant-originalarrivaltime: 02 Aug 2019 10:41:00.8138 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: jerinj@marvell.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR18MB2520 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:5.22.84,1.0.8 definitions=2019-08-02_05:2019-07-31,2019-08-02 signatures=0 Subject: Re: [dpdk-dev] [PATCH v2 02/12] raw/ifpga_rawdev/base: add irq support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Zhang, Tianfei > Sent: Friday, August 2, 2019 3:36 PM > To: Jerin Jacob Kollanukkaran ; Xu, Rosen > ; dev@dpdk.org > Cc: Yigit, Ferruh ; Pei, Andy ; > Lomartire, David ; Zhang, Qi Z > ; Ye, Xiaolong > Subject: [EXT] RE: [dpdk-dev] [PATCH v2 02/12] raw/ifpga_rawdev/base: add > irq support >=20 > > > + > > > +/* only support msix for now*/ > > > +static int vfio_msix_enable_block(s32 vfio_dev_fd, unsigned int > vec_start, > > > + unsigned int count, s32 *fds) > > > > Isn't better to use generic EAL function for the same? >=20 > In our PAC N3000 Card, we have 6 PCIe MSI-X vectors, for example: > 0~3 for AFU > 4 for Port > 6 for FME >=20 > FME (FPGA Management Engine ) will manage all resources in FPGA, like > partition reconfiguration, Power manager, thermal, Error reporting. > Port is a bridge between FME and AFU. > AFU is the accelerator unit which for customers logic. >=20 > So, we reserve some MSI-X vectors for end-user/customers to use the AFU, > and end-user/customers can use the AFU for networking acceleration or > other acceleration. >=20 > The DPDK existing API like rte_intr_enable()->vfio_enable_msix() will bin= d all > of the vectors at the same time and those vectors will register into one > evenfd and one interrupt handler function. > That cannot satisfy our design. we hope that, each MSI-X vector bind into > VFIO and register the interrupt handler function separately. Because the > reserve vectors like > 0~3 vectors for AFU, we don't know what exact usage for the end- > user/customers in AFU logic, so it had better let them bind VFIO and regi= ster > interrupt handler themselves. >=20 > One suggestion is we expand the vfio_enable_msix() function, let the call= er > to specify the start vector and the numbers of vectors to bind the VFIO. Yes, Probably have two variants, vfio_enable_msix() alias to count of 1 > static int > vfio_enable_msix(const struct rte_intr_handle *intr_handle, int start, in= t > count) { > ... > irq_set->count =3D count; > irq_set->start =3D start; > ... > return 0; > } >=20