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d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=HP7BIyw2Y/C8hkvgzZRIvmSm/MyaptHmyY6CakMJdU0=; b=dNHUXYerqWhzK74gGof27tERQU38RpQV80IInzPeauEkcooKCySbuH3g/H4GC29UqP BRyJ4SDqxKXRKlz6ATQYji/wM1yF6eyxRPwzs/SL9f9TziUrm1P7jgVcC4FkZuBLH5Qy mNjryeb27L8r1/SGM6ul5Z1SDOY3lYni6TMt8B4sfZ0MXUiStzrvtjiud/TED/7MKTu3 MXZhqgHI5O29dI1h5P9lgM8ilu72MD3/vjyPVyVKA89cuYIa/eA8cA/kbSkLCxM1TasQ MCz1eREcZKnv9Vd0MfAXeJrEFbZEyBI9QLOsWJ5MW0k9rNflyT48NNiCzEYijH1YX5Zt OXmg== X-Gm-Message-State: AOAM533uKBhtunZtQqP6XsxXdSghusE5JguVBOmQSR7tehBeBAD7hHcY 5fsvxhTTCwsottXy/1GCjfkmcjCVZ78uMk0U6m8Ycw== X-Google-Smtp-Source: ABdhPJwVIXTx8ngi6DSuNnR19unkLPjwJTEgk1hS1LqfoqkdWGyUpA/+44SVaMxijYJ6PhLELxTsrpH9bpACjNB88j0= X-Received: by 2002:adf:e688:: with SMTP id r8mr4324103wrm.274.1589985072196; Wed, 20 May 2020 07:31:12 -0700 (PDT) MIME-Version: 1.0 References: <20200519203419.12369-1-james.quinlan@broadcom.com> <20200519203419.12369-5-james.quinlan@broadcom.com> <5a52e39ce99214877e83104b8ea9f95c0d5b4e90.camel@suse.de> In-Reply-To: <5a52e39ce99214877e83104b8ea9f95c0d5b4e90.camel@suse.de> From: Jim Quinlan Date: Wed, 20 May 2020 10:30:59 -0400 Message-ID: Subject: Re: [PATCH 04/15] PCI: brcmstb: Add compatibily of other chips To: Nicolas Saenz Julienne Cc: Lorenzo Pieralisi , Rob Herring , Bjorn Helgaas , Florian Fainelli , "maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE" , "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" , "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" , "open list:PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS" , open list Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, May 20, 2020 at 7:51 AM Nicolas Saenz Julienne wrote: > > Hi Jim, > > On Tue, 2020-05-19 at 16:34 -0400, Jim Quinlan wrote: > > From: Jim Quinlan > > > > Add in compatibility strings and code for three Broadcom STB chips. > > Some of the register locations, shifts, and masks are different > > for certain chips, requiring the use of different constants based > > on of_id. > > > > We would like to add the following at this time to the match list > > but we need to wait until the end of this patchset so that > > everything works. > > > > { .compatible = "brcm,bcm7211-pcie", .data = &generic_cfg }, > > { .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg }, > > { .compatible = "brcm,bcm7216-pcie", .data = &bcm7278_cfg }, > > { .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg }, > > > > Signed-off-by: Jim Quinlan > > --- > > drivers/pci/controller/pcie-brcmstb.c | 103 +++++++++++++++++++++++--- > > 1 file changed, 91 insertions(+), 12 deletions(-) > > > > diff --git a/drivers/pci/controller/pcie-brcmstb.c > > b/drivers/pci/controller/pcie-brcmstb.c > > index 73020b4ff090..c1cf4ea7d3d9 100644 > > --- a/drivers/pci/controller/pcie-brcmstb.c > > +++ b/drivers/pci/controller/pcie-brcmstb.c > > @@ -120,9 +120,8 @@ > > #define PCIE_EXT_SLOT_SHIFT 15 > > #define PCIE_EXT_FUNC_SHIFT 12 > > > > -#define PCIE_RGR1_SW_INIT_1 0x9210 > > #define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1 > > -#define PCIE_RGR1_SW_INIT_1_INIT_MASK 0x2 > > +#define PCIE_RGR1_SW_INIT_1_PERST_SHIFT 0x0 > > > > /* PCIe parameters */ > > #define BRCM_NUM_PCIE_OUT_WINS 0x4 > > @@ -152,6 +151,69 @@ > > #define SSC_STATUS_SSC_MASK 0x400 > > #define SSC_STATUS_PLL_LOCK_MASK 0x800 > > > > +#define IDX_ADDR(pcie) \ > > + (pcie->reg_offsets[EXT_CFG_INDEX]) > > +#define DATA_ADDR(pcie) \ > > + (pcie->reg_offsets[EXT_CFG_DATA]) > > +#define PCIE_RGR1_SW_INIT_1(pcie) \ > > + (pcie->reg_offsets[RGR1_SW_INIT_1]) > > + > > +enum { > > + RGR1_SW_INIT_1, > > + EXT_CFG_INDEX, > > + EXT_CFG_DATA, > > +}; > > + > > +enum { > > + RGR1_SW_INIT_1_INIT_MASK, > > + RGR1_SW_INIT_1_INIT_SHIFT, > > +}; > > + > > +enum pcie_type { > > + GENERIC, > > + BCM7278, > > +}; > > + > > +struct pcie_cfg_data { > > + const int *reg_field_info; > > + const int *offsets; > > + const enum pcie_type type; > > +}; > > + > > +static const int pcie_reg_field_info[] = { > > + [RGR1_SW_INIT_1_INIT_MASK] = 0x2, > > + [RGR1_SW_INIT_1_INIT_SHIFT] = 0x1, > > +}; > > + > > +static const int pcie_reg_field_info_bcm7278[] = { > > + [RGR1_SW_INIT_1_INIT_MASK] = 0x1, > > + [RGR1_SW_INIT_1_INIT_SHIFT] = 0x0, > > +}; > > + > > +static const int pcie_offsets[] = { > > + [RGR1_SW_INIT_1] = 0x9210, > > + [EXT_CFG_INDEX] = 0x9000, > > + [EXT_CFG_DATA] = 0x9004, > > +}; > > + > > +static const struct pcie_cfg_data generic_cfg = { > > + .reg_field_info = pcie_reg_field_info, > > + .offsets = pcie_offsets, > > + .type = GENERIC, > > +}; > > + > > +static const int pcie_offset_bcm7278[] = { > > + [RGR1_SW_INIT_1] = 0xc010, > > + [EXT_CFG_INDEX] = 0x9000, > > + [EXT_CFG_DATA] = 0x9004, > > +}; > > + > > +static const struct pcie_cfg_data bcm7278_cfg = { > > + .reg_field_info = pcie_reg_field_info_bcm7278, > > + .offsets = pcie_offset_bcm7278, > > + .type = BCM7278, > > +}; > > It's not essential, but if v2 is due I'd suggest factoring out the bcm2728 > specific structures above, and moving them to patch #15. This will keep a > clearer division between the patch introducing the infrastructure and the one > adding the support for a new device. The problem is that one of the commits needs the 7278 type so it has to be declared earlier. > > > + > > struct brcm_msi { > > struct device *dev; > > void __iomem *base; > > @@ -176,6 +238,9 @@ struct brcm_pcie { > > int gen; > > u64 msi_target_addr; > > struct brcm_msi *msi; > > + const int *reg_offsets; > > + const int *reg_field_info; > > + enum pcie_type type; > > }; > > > > /* > > @@ -602,20 +667,21 @@ static struct pci_ops brcm_pcie_ops = { > > > > static inline void brcm_pcie_bridge_sw_init_set(struct brcm_pcie *pcie, u32 > > val) > > { > > - u32 tmp; > > + u32 tmp, mask = pcie->reg_field_info[RGR1_SW_INIT_1_INIT_MASK]; > > + u32 shift = pcie->reg_field_info[RGR1_SW_INIT_1_INIT_SHIFT]; > > I don't think you need shift here, IIUC u32p_replace_bits() will take care of > all the masking and shifting internally, moreover, you'd be able to drop the > shift entry from reg_field_info. Got it. > > > - tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1); > > - u32p_replace_bits(&tmp, val, PCIE_RGR1_SW_INIT_1_INIT_MASK); > > - writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1); > > + tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); > > + tmp = (tmp & ~mask) | ((val << shift) & mask); > > + writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); > > } > > Regards, > Nicolas > Thanks! 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h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=HP7BIyw2Y/C8hkvgzZRIvmSm/MyaptHmyY6CakMJdU0=; b=bHrHbHuozecq6TGEmkGaTlaGPQ+GQ3/CW+L0OcHr3s9rZ2jl8iJmAvvWuObDfD7TrK RCNo6AkPk2O1kpnQo4/RBxzNeo4d+bF9T8Y562+MQgAbdjFricr1ExRk7I/QMa2wNC9F gb1hsZfX2o30zCJZHtpvxVR44eJJEf1Ymf435KWkkPmeiXI9mibJAVBDHQi734cnw/oI dXNmDVisGZY6CnYTETB+vhXJL3e6Py1CYMamsdmtPeGOpIryRuvDMxXDHUFpGiXhx9pN QchwJoF5DsjcPr3yT/aWe57NOpPlQcNAJPhgPlmbumowQdCWlbti1QgXsTdoPkpyx0jl P5rQ== X-Gm-Message-State: AOAM532tixYSvKAkXnfyT1VMM17n9cHA7U75uHCWu/z4ws3iOQNRMu1E /dEzsuvgp0SCHj0gWLHLrffRvdP5ouXtMOS6S/q5Sw== X-Google-Smtp-Source: ABdhPJwVIXTx8ngi6DSuNnR19unkLPjwJTEgk1hS1LqfoqkdWGyUpA/+44SVaMxijYJ6PhLELxTsrpH9bpACjNB88j0= X-Received: by 2002:adf:e688:: with SMTP id r8mr4324103wrm.274.1589985072196; Wed, 20 May 2020 07:31:12 -0700 (PDT) MIME-Version: 1.0 References: <20200519203419.12369-1-james.quinlan@broadcom.com> <20200519203419.12369-5-james.quinlan@broadcom.com> <5a52e39ce99214877e83104b8ea9f95c0d5b4e90.camel@suse.de> In-Reply-To: <5a52e39ce99214877e83104b8ea9f95c0d5b4e90.camel@suse.de> From: Jim Quinlan Date: Wed, 20 May 2020 10:30:59 -0400 Message-ID: Subject: Re: [PATCH 04/15] PCI: brcmstb: Add compatibily of other chips To: Nicolas Saenz Julienne X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200520_073116_227510_E98AC166 X-CRM114-Status: GOOD ( 24.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Herring , Lorenzo Pieralisi , "open list:PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS" , open list , Florian Fainelli , "maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE" , "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" , Bjorn Helgaas , "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, May 20, 2020 at 7:51 AM Nicolas Saenz Julienne wrote: > > Hi Jim, > > On Tue, 2020-05-19 at 16:34 -0400, Jim Quinlan wrote: > > From: Jim Quinlan > > > > Add in compatibility strings and code for three Broadcom STB chips. > > Some of the register locations, shifts, and masks are different > > for certain chips, requiring the use of different constants based > > on of_id. > > > > We would like to add the following at this time to the match list > > but we need to wait until the end of this patchset so that > > everything works. > > > > { .compatible = "brcm,bcm7211-pcie", .data = &generic_cfg }, > > { .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg }, > > { .compatible = "brcm,bcm7216-pcie", .data = &bcm7278_cfg }, > > { .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg }, > > > > Signed-off-by: Jim Quinlan > > --- > > drivers/pci/controller/pcie-brcmstb.c | 103 +++++++++++++++++++++++--- > > 1 file changed, 91 insertions(+), 12 deletions(-) > > > > diff --git a/drivers/pci/controller/pcie-brcmstb.c > > b/drivers/pci/controller/pcie-brcmstb.c > > index 73020b4ff090..c1cf4ea7d3d9 100644 > > --- a/drivers/pci/controller/pcie-brcmstb.c > > +++ b/drivers/pci/controller/pcie-brcmstb.c > > @@ -120,9 +120,8 @@ > > #define PCIE_EXT_SLOT_SHIFT 15 > > #define PCIE_EXT_FUNC_SHIFT 12 > > > > -#define PCIE_RGR1_SW_INIT_1 0x9210 > > #define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1 > > -#define PCIE_RGR1_SW_INIT_1_INIT_MASK 0x2 > > +#define PCIE_RGR1_SW_INIT_1_PERST_SHIFT 0x0 > > > > /* PCIe parameters */ > > #define BRCM_NUM_PCIE_OUT_WINS 0x4 > > @@ -152,6 +151,69 @@ > > #define SSC_STATUS_SSC_MASK 0x400 > > #define SSC_STATUS_PLL_LOCK_MASK 0x800 > > > > +#define IDX_ADDR(pcie) \ > > + (pcie->reg_offsets[EXT_CFG_INDEX]) > > +#define DATA_ADDR(pcie) \ > > + (pcie->reg_offsets[EXT_CFG_DATA]) > > +#define PCIE_RGR1_SW_INIT_1(pcie) \ > > + (pcie->reg_offsets[RGR1_SW_INIT_1]) > > + > > +enum { > > + RGR1_SW_INIT_1, > > + EXT_CFG_INDEX, > > + EXT_CFG_DATA, > > +}; > > + > > +enum { > > + RGR1_SW_INIT_1_INIT_MASK, > > + RGR1_SW_INIT_1_INIT_SHIFT, > > +}; > > + > > +enum pcie_type { > > + GENERIC, > > + BCM7278, > > +}; > > + > > +struct pcie_cfg_data { > > + const int *reg_field_info; > > + const int *offsets; > > + const enum pcie_type type; > > +}; > > + > > +static const int pcie_reg_field_info[] = { > > + [RGR1_SW_INIT_1_INIT_MASK] = 0x2, > > + [RGR1_SW_INIT_1_INIT_SHIFT] = 0x1, > > +}; > > + > > +static const int pcie_reg_field_info_bcm7278[] = { > > + [RGR1_SW_INIT_1_INIT_MASK] = 0x1, > > + [RGR1_SW_INIT_1_INIT_SHIFT] = 0x0, > > +}; > > + > > +static const int pcie_offsets[] = { > > + [RGR1_SW_INIT_1] = 0x9210, > > + [EXT_CFG_INDEX] = 0x9000, > > + [EXT_CFG_DATA] = 0x9004, > > +}; > > + > > +static const struct pcie_cfg_data generic_cfg = { > > + .reg_field_info = pcie_reg_field_info, > > + .offsets = pcie_offsets, > > + .type = GENERIC, > > +}; > > + > > +static const int pcie_offset_bcm7278[] = { > > + [RGR1_SW_INIT_1] = 0xc010, > > + [EXT_CFG_INDEX] = 0x9000, > > + [EXT_CFG_DATA] = 0x9004, > > +}; > > + > > +static const struct pcie_cfg_data bcm7278_cfg = { > > + .reg_field_info = pcie_reg_field_info_bcm7278, > > + .offsets = pcie_offset_bcm7278, > > + .type = BCM7278, > > +}; > > It's not essential, but if v2 is due I'd suggest factoring out the bcm2728 > specific structures above, and moving them to patch #15. This will keep a > clearer division between the patch introducing the infrastructure and the one > adding the support for a new device. The problem is that one of the commits needs the 7278 type so it has to be declared earlier. > > > + > > struct brcm_msi { > > struct device *dev; > > void __iomem *base; > > @@ -176,6 +238,9 @@ struct brcm_pcie { > > int gen; > > u64 msi_target_addr; > > struct brcm_msi *msi; > > + const int *reg_offsets; > > + const int *reg_field_info; > > + enum pcie_type type; > > }; > > > > /* > > @@ -602,20 +667,21 @@ static struct pci_ops brcm_pcie_ops = { > > > > static inline void brcm_pcie_bridge_sw_init_set(struct brcm_pcie *pcie, u32 > > val) > > { > > - u32 tmp; > > + u32 tmp, mask = pcie->reg_field_info[RGR1_SW_INIT_1_INIT_MASK]; > > + u32 shift = pcie->reg_field_info[RGR1_SW_INIT_1_INIT_SHIFT]; > > I don't think you need shift here, IIUC u32p_replace_bits() will take care of > all the masking and shifting internally, moreover, you'd be able to drop the > shift entry from reg_field_info. Got it. > > > - tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1); > > - u32p_replace_bits(&tmp, val, PCIE_RGR1_SW_INIT_1_INIT_MASK); > > - writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1); > > + tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); > > + tmp = (tmp & ~mask) | ((val << shift) & mask); > > + writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); > > } > > Regards, > Nicolas > Thanks! Jim _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel