Re: [PATCH V2 01/12] spi/mxs: Always set LOCK_CS

[Trent Piepho <tpiepho-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]

On Wed, Jul 10, 2013 at 8:29 AM, Lothar Waßmann <LW-AvR2QvxeiV7DiMYJYoSAnRvVK+yQ3ZXh@public.gmane.org>wrote:

> > >> always be set.  The DMA code will always set it, explicitly on the
> > >> first segment of the first transfer, and then implicitly on all the
> > >> rest by never clearing the bit from the value read from the ctrl0
> > >> register.
> > >>
> > >> The only reason to not set LOCK_CS would be to attempt an altered
> > >> protocol where CS pulses between each word.  Though don't get your
> > >> hopes up if you want to do this, as the hardware doesn't appear to do
> > >> this in any sane manner.
> > >
> > > Can you please elaborate on this part above? The description is very
> vague.
> > >
> > >> LOCK_CS keeps CS asserted though the entire transfer.  This should
> From my experience the HW deasserts CS whenever the output fifo runs
> empty.
>
>
I think that might be the case.  Since I have no need to add support for
some non-standard SPI protocol nobody has wanted, I didn't spend the time
to reverse engineer how exactly it worked.  I think what would happen is
that if you used multi-word transfers (and the current PIO mode in the
driver ONLY uses single word transfers!) you would sometimes get a CS pulse
between each word and sometimes every four words.  It seemed to make a
difference if one used multi-word PIO with a FIFO, which the current driver
doesn't support, or multi-word DMA.

I did spend enough time on it to determine that, "always set LOCK_CS all
the time for normal SPI," is correct.  The driver's method of setting in
for all transfers but the last, except in DMA mode where it's set on the
last transfer too, apparently by accident, is unnecessarily complex and
inefficient.  It only "works" because the current PIO code only supports
single word transfers at the hardware level.
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