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[209.85.167.181]) by smtp.gmail.com with ESMTPSA id m20sm89688oiw.46.2021.09.01.12.41.10 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 01 Sep 2021 12:41:10 -0700 (PDT) Received: by mail-oi1-f181.google.com with SMTP id q39so743674oiw.12 for ; Wed, 01 Sep 2021 12:41:10 -0700 (PDT) X-Received: by 2002:aca:5344:: with SMTP id h65mr992912oib.117.1630525269918; Wed, 01 Sep 2021 12:41:09 -0700 (PDT) MIME-Version: 1.0 References: <20210830123704.221494-1-verdre@v0yd.nl> <20210830123704.221494-2-verdre@v0yd.nl> In-Reply-To: <20210830123704.221494-2-verdre@v0yd.nl> From: Brian Norris Date: Wed, 1 Sep 2021 12:40:58 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 1/2] mwifiex: Use non-posted PCI register writes To: =?UTF-8?Q?Jonas_Dre=C3=9Fler?= Cc: Amitkumar Karwar , Ganapathi Bhat , Xinming Hu , Kalle Valo , "David S. Miller" , Jakub Kicinski , Tsuchiya Yuto , linux-wireless , "" , Linux Kernel , linux-pci@vger.kernel.org, Maximilian Luz , Andy Shevchenko , Bjorn Helgaas , =?UTF-8?Q?Pali_Roh=C3=A1r?= Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org On Mon, Aug 30, 2021 at 5:37 AM Jonas Dre=C3=9Fler wrote: > > On the 88W8897 card it's very important the TX ring write pointer is > updated correctly to its new value before setting the TX ready > interrupt, otherwise the firmware appears to crash (probably because > it's trying to DMA-read from the wrong place). > > Since PCI uses "posted writes" when writing to a register, it's not > guaranteed that a write will happen immediately. That means the pointer > might be outdated when setting the TX ready interrupt, leading to > firmware crashes especially when ASPM L1 and L1 substates are enabled > (because of the higher link latency, the write will probably take > longer). > > So fix those firmware crashes by always forcing non-posted writes. We do > that by simply reading back the register after writing it, just as a lot > of other drivers do. > > There are two reproducers that are fixed with this patch: > > 1) During rx/tx traffic and with ASPM L1 substates enabled (the enabled > substates are platform dependent), the firmware crashes and eventually a > command timeout appears in the logs. That crash is fixed by using a > non-posted write in mwifiex_pcie_send_data(). > > 2) When sending lots of commands to the card, waking it up from sleep in > very quick intervals, the firmware eventually crashes. That crash > appears to be fixed by some other non-posted write included here. > > Signed-off-by: Jonas Dre=C3=9Fler This might be good for many cases, but please read this commit: https://git.kernel.org/linus/062e008a6e83e7c4da7df0a9c6aefdbc849e2bb3 mwifiex: pcie: use posted write to wake up firmware It's very much intentional that this is a posted write in some cases. Without ensuring this doesn't regress, NAK from me. Brian