[PATCH 0/7] Timer & SPI support for Allwinner suniv F1C100s

[PATCH 0/7] Timer & SPI support for Allwinner suniv F1C100s

[Mesih Kilinc]

This is followup series for F1C100s initial support patchset. 
All patches merged except patch 1 ~ 2 which is related to timer.
I am resending those since they are already have Acked tags.

Our dt-bindings for F1C100s are merged, we can now use them at our 
device tree source - patch 3.

Also this series add spi support and enables spi flash at Lichee-pi Nano
in patch 4 ~ 7. This patches are based on Icenowy's work.

Thanks!

Mesih Kilinc (7):
  dt-bindings: timer: Add Allwinner suniv timer
  clocksource: sun4i: add a compatible for suniv
  ARM: dts: suniv: Add dt-binding headers for F1C100s
  dt-bindings: spi: Add Support for Allwinner F1C100s
  ARM: dts: suniv: Add SPI device-tree nodes
  ARM: dts: suniv: Add pinmux for SPI0 and SPI1 of F1C100s
  ARM: dts: f1c100s: Activate SPI flash on Lichee Pi Nano

 .../devicetree/bindings/spi/spi-sun6i.txt          |  5 +-
 .../bindings/timer/allwinner,sun4i-timer.txt       |  4 +-
 arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts  | 13 ++++++
 arch/arm/boot/dts/suniv-f1c100s.dtsi               | 53 +++++++++++++++++++---
 drivers/clocksource/timer-sun4i.c                  |  5 +-
 5 files changed, 70 insertions(+), 10 deletions(-)

-- 
2.7.4

[PATCH 0/7] Timer & SPI support for Allwinner suniv F1C100s

[Mesih Kilinc]

This is followup series for F1C100s initial support patchset. 
All patches merged except patch 1 ~ 2 which is related to timer.
I am resending those since they are already have Acked tags.

Our dt-bindings for F1C100s are merged, we can now use them at our 
device tree source - patch 3.

Also this series add spi support and enables spi flash at Lichee-pi Nano
in patch 4 ~ 7. This patches are based on Icenowy's work.

Thanks!

Mesih Kilinc (7):
  dt-bindings: timer: Add Allwinner suniv timer
  clocksource: sun4i: add a compatible for suniv
  ARM: dts: suniv: Add dt-binding headers for F1C100s
  dt-bindings: spi: Add Support for Allwinner F1C100s
  ARM: dts: suniv: Add SPI device-tree nodes
  ARM: dts: suniv: Add pinmux for SPI0 and SPI1 of F1C100s
  ARM: dts: f1c100s: Activate SPI flash on Lichee Pi Nano

 .../devicetree/bindings/spi/spi-sun6i.txt          |  5 +-
 .../bindings/timer/allwinner,sun4i-timer.txt       |  4 +-
 arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts  | 13 ++++++
 arch/arm/boot/dts/suniv-f1c100s.dtsi               | 53 +++++++++++++++++++---
 drivers/clocksource/timer-sun4i.c                  |  5 +-
 5 files changed, 70 insertions(+), 10 deletions(-)

-- 
2.7.4


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[PATCH 1/7] dt-bindings: timer: Add Allwinner suniv timer

[Mesih Kilinc]

Add compatible string for Allwinner suniv timer which is similar to
sun4i timer.

Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt b/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt
index 5c2e235..3da9d51 100644
--- a/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt
+++ b/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt
@@ -2,7 +2,9 @@ Allwinner A1X SoCs Timer Controller
 
 Required properties:
 
-- compatible : should be "allwinner,sun4i-a10-timer"
+- compatible : should be one of the following:
+              "allwinner,sun4i-a10-timer"
+              "allwinner,suniv-f1c100s-timer"
 - reg : Specifies base physical address and size of the registers.
 - interrupts : The interrupt of the first timer
 - clocks: phandle to the source clock (usually a 24 MHz fixed clock)
-- 
2.7.4

[PATCH 1/7] dt-bindings: timer: Add Allwinner suniv timer

[Mesih Kilinc]

Add compatible string for Allwinner suniv timer which is similar to
sun4i timer.

Signed-off-by: Mesih Kilinc <mesihkilinc-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Acked-by: Maxime Ripard <maxime.ripard-LDxbnhwyfcJBDgjK7y7TUQ@public.gmane.org>
Reviewed-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
---
 Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt b/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt
index 5c2e235..3da9d51 100644
--- a/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt
+++ b/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt
@@ -2,7 +2,9 @@ Allwinner A1X SoCs Timer Controller
 
 Required properties:
 
-- compatible : should be "allwinner,sun4i-a10-timer"
+- compatible : should be one of the following:
+              "allwinner,sun4i-a10-timer"
+              "allwinner,suniv-f1c100s-timer"
 - reg : Specifies base physical address and size of the registers.
 - interrupts : The interrupt of the first timer
 - clocks: phandle to the source clock (usually a 24 MHz fixed clock)
-- 
2.7.4

[PATCH 1/7] dt-bindings: timer: Add Allwinner suniv timer

[Mesih Kilinc]

Add compatible string for Allwinner suniv timer which is similar to
sun4i timer.

Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt b/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt
index 5c2e235..3da9d51 100644
--- a/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt
+++ b/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt
@@ -2,7 +2,9 @@ Allwinner A1X SoCs Timer Controller
 
 Required properties:
 
-- compatible : should be "allwinner,sun4i-a10-timer"
+- compatible : should be one of the following:
+              "allwinner,sun4i-a10-timer"
+              "allwinner,suniv-f1c100s-timer"
 - reg : Specifies base physical address and size of the registers.
 - interrupts : The interrupt of the first timer
 - clocks: phandle to the source clock (usually a 24 MHz fixed clock)
-- 
2.7.4


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[PATCH 2/7] clocksource: sun4i: add a compatible for suniv

[Mesih Kilinc]

The suniv (new F-series) chip has a timer with less functionality than
the A10 timer, e.g. it has only 3 channels.

Add a new compatible for it. As we didn't use the extra channels on A10
either now, the code needn't to be changed.

The suniv chip is based on ARM926EJ-S CPU, thus it has no architecture timer.

Register sun4i_timer as sched_clock on it.

Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
 drivers/clocksource/timer-sun4i.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/clocksource/timer-sun4i.c b/drivers/clocksource/timer-sun4i.c
index 6e0180a..65f38f6 100644
--- a/drivers/clocksource/timer-sun4i.c
+++ b/drivers/clocksource/timer-sun4i.c
@@ -186,7 +186,8 @@ static int __init sun4i_timer_init(struct device_node *node)
 	 */
 	if (of_machine_is_compatible("allwinner,sun4i-a10") ||
 	    of_machine_is_compatible("allwinner,sun5i-a13") ||
-	    of_machine_is_compatible("allwinner,sun5i-a10s"))
+	    of_machine_is_compatible("allwinner,sun5i-a10s") ||
+	    of_machine_is_compatible("allwinner,suniv-f1c100s"))
 		sched_clock_register(sun4i_timer_sched_read, 32,
 				     timer_of_rate(&to));
 
@@ -218,3 +219,5 @@ static int __init sun4i_timer_init(struct device_node *node)
 }
 TIMER_OF_DECLARE(sun4i, "allwinner,sun4i-a10-timer",
 		       sun4i_timer_init);
+TIMER_OF_DECLARE(suniv, "allwinner,suniv-f1c100s-timer",
+		       sun4i_timer_init);
-- 
2.7.4

[PATCH 2/7] clocksource: sun4i: add a compatible for suniv

[Mesih Kilinc]

The suniv (new F-series) chip has a timer with less functionality than
the A10 timer, e.g. it has only 3 channels.

Add a new compatible for it. As we didn't use the extra channels on A10
either now, the code needn't to be changed.

The suniv chip is based on ARM926EJ-S CPU, thus it has no architecture timer.

Register sun4i_timer as sched_clock on it.

Signed-off-by: Mesih Kilinc <mesihkilinc-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Acked-by: Maxime Ripard <maxime.ripard-LDxbnhwyfcJBDgjK7y7TUQ@public.gmane.org>
Acked-by: Daniel Lezcano <daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
 drivers/clocksource/timer-sun4i.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/clocksource/timer-sun4i.c b/drivers/clocksource/timer-sun4i.c
index 6e0180a..65f38f6 100644
--- a/drivers/clocksource/timer-sun4i.c
+++ b/drivers/clocksource/timer-sun4i.c
@@ -186,7 +186,8 @@ static int __init sun4i_timer_init(struct device_node *node)
 	 */
 	if (of_machine_is_compatible("allwinner,sun4i-a10") ||
 	    of_machine_is_compatible("allwinner,sun5i-a13") ||
-	    of_machine_is_compatible("allwinner,sun5i-a10s"))
+	    of_machine_is_compatible("allwinner,sun5i-a10s") ||
+	    of_machine_is_compatible("allwinner,suniv-f1c100s"))
 		sched_clock_register(sun4i_timer_sched_read, 32,
 				     timer_of_rate(&to));
 
@@ -218,3 +219,5 @@ static int __init sun4i_timer_init(struct device_node *node)
 }
 TIMER_OF_DECLARE(sun4i, "allwinner,sun4i-a10-timer",
 		       sun4i_timer_init);
+TIMER_OF_DECLARE(suniv, "allwinner,suniv-f1c100s-timer",
+		       sun4i_timer_init);
-- 
2.7.4

[PATCH 2/7] clocksource: sun4i: add a compatible for suniv

[Mesih Kilinc]

The suniv (new F-series) chip has a timer with less functionality than
the A10 timer, e.g. it has only 3 channels.

Add a new compatible for it. As we didn't use the extra channels on A10
either now, the code needn't to be changed.

The suniv chip is based on ARM926EJ-S CPU, thus it has no architecture timer.

Register sun4i_timer as sched_clock on it.

Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
 drivers/clocksource/timer-sun4i.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/clocksource/timer-sun4i.c b/drivers/clocksource/timer-sun4i.c
index 6e0180a..65f38f6 100644
--- a/drivers/clocksource/timer-sun4i.c
+++ b/drivers/clocksource/timer-sun4i.c
@@ -186,7 +186,8 @@ static int __init sun4i_timer_init(struct device_node *node)
 	 */
 	if (of_machine_is_compatible("allwinner,sun4i-a10") ||
 	    of_machine_is_compatible("allwinner,sun5i-a13") ||
-	    of_machine_is_compatible("allwinner,sun5i-a10s"))
+	    of_machine_is_compatible("allwinner,sun5i-a10s") ||
+	    of_machine_is_compatible("allwinner,suniv-f1c100s"))
 		sched_clock_register(sun4i_timer_sched_read, 32,
 				     timer_of_rate(&to));
 
@@ -218,3 +219,5 @@ static int __init sun4i_timer_init(struct device_node *node)
 }
 TIMER_OF_DECLARE(sun4i, "allwinner,sun4i-a10-timer",
 		       sun4i_timer_init);
+TIMER_OF_DECLARE(suniv, "allwinner,suniv-f1c100s-timer",
+		       sun4i_timer_init);
-- 
2.7.4


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[PATCH 3/7] ARM: dts: suniv: Add dt-binding headers for F1C100s

[Mesih Kilinc]

dt-binding headers for F1C100s merged now. So add them back to dtsi.

Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
---
 arch/arm/boot/dts/suniv-f1c100s.dtsi | 17 ++++++++++-------
 1 file changed, 10 insertions(+), 7 deletions(-)

diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
index 6100d3b..953228c 100644
--- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
+++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
@@ -4,6 +4,9 @@
  * Copyright 2018 Mesih Kilinc <mesihkilinc@gmail.com>
  */
 
+#include <dt-bindings/clock/suniv-ccu-f1c100s.h>
+#include <dt-bindings/reset/suniv-ccu-f1c100s.h>
+
 / {
 	#address-cells = <1>;
 	#size-cells = <1>;
@@ -82,7 +85,7 @@
 			compatible = "allwinner,suniv-f1c100s-pinctrl";
 			reg = <0x01c20800 0x400>;
 			interrupts = <38>, <39>, <40>;
-			clocks = <&ccu 37>, <&osc24M>, <&osc32k>;
+			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
 			clock-names = "apb", "hosc", "losc";
 			gpio-controller;
 			interrupt-controller;
@@ -114,8 +117,8 @@
 			interrupts = <1>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
-			clocks = <&ccu 38>;
-			resets = <&ccu 24>;
+			clocks = <&ccu CLK_BUS_UART0>;
+			resets = <&ccu RST_BUS_UART0>;
 			status = "disabled";
 		};
 
@@ -125,8 +128,8 @@
 			interrupts = <2>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
-			clocks = <&ccu 39>;
-			resets = <&ccu 25>;
+			clocks = <&ccu CLK_BUS_UART1>;
+			resets = <&ccu RST_BUS_UART1>;
 			status = "disabled";
 		};
 
@@ -136,8 +139,8 @@
 			interrupts = <3>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
-			clocks = <&ccu 40>;
-			resets = <&ccu 26>;
+			clocks = <&ccu CLK_BUS_UART2>;
+			resets = <&ccu RST_BUS_UART2>;
 			status = "disabled";
 		};
 	};
-- 
2.7.4

[PATCH 3/7] ARM: dts: suniv: Add dt-binding headers for F1C100s

[Mesih Kilinc]

dt-binding headers for F1C100s merged now. So add them back to dtsi.

Signed-off-by: Mesih Kilinc <mesihkilinc-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 arch/arm/boot/dts/suniv-f1c100s.dtsi | 17 ++++++++++-------
 1 file changed, 10 insertions(+), 7 deletions(-)

diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
index 6100d3b..953228c 100644
--- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
+++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
@@ -4,6 +4,9 @@
  * Copyright 2018 Mesih Kilinc <mesihkilinc-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
  */
 
+#include <dt-bindings/clock/suniv-ccu-f1c100s.h>
+#include <dt-bindings/reset/suniv-ccu-f1c100s.h>
+
 / {
 	#address-cells = <1>;
 	#size-cells = <1>;
@@ -82,7 +85,7 @@
 			compatible = "allwinner,suniv-f1c100s-pinctrl";
 			reg = <0x01c20800 0x400>;
 			interrupts = <38>, <39>, <40>;
-			clocks = <&ccu 37>, <&osc24M>, <&osc32k>;
+			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
 			clock-names = "apb", "hosc", "losc";
 			gpio-controller;
 			interrupt-controller;
@@ -114,8 +117,8 @@
 			interrupts = <1>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
-			clocks = <&ccu 38>;
-			resets = <&ccu 24>;
+			clocks = <&ccu CLK_BUS_UART0>;
+			resets = <&ccu RST_BUS_UART0>;
 			status = "disabled";
 		};
 
@@ -125,8 +128,8 @@
 			interrupts = <2>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
-			clocks = <&ccu 39>;
-			resets = <&ccu 25>;
+			clocks = <&ccu CLK_BUS_UART1>;
+			resets = <&ccu RST_BUS_UART1>;
 			status = "disabled";
 		};
 
@@ -136,8 +139,8 @@
 			interrupts = <3>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
-			clocks = <&ccu 40>;
-			resets = <&ccu 26>;
+			clocks = <&ccu CLK_BUS_UART2>;
+			resets = <&ccu RST_BUS_UART2>;
 			status = "disabled";
 		};
 	};
-- 
2.7.4

[PATCH 3/7] ARM: dts: suniv: Add dt-binding headers for F1C100s

[Mesih Kilinc]

dt-binding headers for F1C100s merged now. So add them back to dtsi.

Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
---
 arch/arm/boot/dts/suniv-f1c100s.dtsi | 17 ++++++++++-------
 1 file changed, 10 insertions(+), 7 deletions(-)

diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
index 6100d3b..953228c 100644
--- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
+++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
@@ -4,6 +4,9 @@
  * Copyright 2018 Mesih Kilinc <mesihkilinc@gmail.com>
  */
 
+#include <dt-bindings/clock/suniv-ccu-f1c100s.h>
+#include <dt-bindings/reset/suniv-ccu-f1c100s.h>
+
 / {
 	#address-cells = <1>;
 	#size-cells = <1>;
@@ -82,7 +85,7 @@
 			compatible = "allwinner,suniv-f1c100s-pinctrl";
 			reg = <0x01c20800 0x400>;
 			interrupts = <38>, <39>, <40>;
-			clocks = <&ccu 37>, <&osc24M>, <&osc32k>;
+			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
 			clock-names = "apb", "hosc", "losc";
 			gpio-controller;
 			interrupt-controller;
@@ -114,8 +117,8 @@
 			interrupts = <1>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
-			clocks = <&ccu 38>;
-			resets = <&ccu 24>;
+			clocks = <&ccu CLK_BUS_UART0>;
+			resets = <&ccu RST_BUS_UART0>;
 			status = "disabled";
 		};
 
@@ -125,8 +128,8 @@
 			interrupts = <2>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
-			clocks = <&ccu 39>;
-			resets = <&ccu 25>;
+			clocks = <&ccu CLK_BUS_UART1>;
+			resets = <&ccu RST_BUS_UART1>;
 			status = "disabled";
 		};
 
@@ -136,8 +139,8 @@
 			interrupts = <3>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
-			clocks = <&ccu 40>;
-			resets = <&ccu 26>;
+			clocks = <&ccu CLK_BUS_UART2>;
+			resets = <&ccu RST_BUS_UART2>;
 			status = "disabled";
 		};
 	};
-- 
2.7.4


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[PATCH 4/7] dt-bindings: spi: Add Support for Allwinner F1C100s

[Mesih Kilinc]

Allwinner suniv F1C100s has similar SPI controllers as sun8i H3.
Add compatible string for it.

Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
---
 Documentation/devicetree/bindings/spi/spi-sun6i.txt | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/spi/spi-sun6i.txt b/Documentation/devicetree/bindings/spi/spi-sun6i.txt
index 435a8e0..33f490f 100644
--- a/Documentation/devicetree/bindings/spi/spi-sun6i.txt
+++ b/Documentation/devicetree/bindings/spi/spi-sun6i.txt
@@ -1,7 +1,10 @@
 Allwinner A31/H3 SPI controller
 
 Required properties:
-- compatible: Should be "allwinner,sun6i-a31-spi" or "allwinner,sun8i-h3-spi".
+- compatible: should be:
+	- "allwinner,sun6i-a31-spi"
+	- "allwinner,sun8i-h3-spi"
+	- "allwinner,suniv-f1c100s-spi", "allwinner,sun8i-h3-spi"
 - reg: Should contain register location and length.
 - interrupts: Should contain interrupt.
 - clocks: phandle to the clocks feeding the SPI controller. Two are
-- 
2.7.4

[PATCH 4/7] dt-bindings: spi: Add Support for Allwinner F1C100s

[Mesih Kilinc]

Allwinner suniv F1C100s has similar SPI controllers as sun8i H3.
Add compatible string for it.

Signed-off-by: Mesih Kilinc <mesihkilinc-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 Documentation/devicetree/bindings/spi/spi-sun6i.txt | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/spi/spi-sun6i.txt b/Documentation/devicetree/bindings/spi/spi-sun6i.txt
index 435a8e0..33f490f 100644
--- a/Documentation/devicetree/bindings/spi/spi-sun6i.txt
+++ b/Documentation/devicetree/bindings/spi/spi-sun6i.txt
@@ -1,7 +1,10 @@
 Allwinner A31/H3 SPI controller
 
 Required properties:
-- compatible: Should be "allwinner,sun6i-a31-spi" or "allwinner,sun8i-h3-spi".
+- compatible: should be:
+	- "allwinner,sun6i-a31-spi"
+	- "allwinner,sun8i-h3-spi"
+	- "allwinner,suniv-f1c100s-spi", "allwinner,sun8i-h3-spi"
 - reg: Should contain register location and length.
 - interrupts: Should contain interrupt.
 - clocks: phandle to the clocks feeding the SPI controller. Two are
-- 
2.7.4

[PATCH 4/7] dt-bindings: spi: Add Support for Allwinner F1C100s

[Mesih Kilinc]

Allwinner suniv F1C100s has similar SPI controllers as sun8i H3.
Add compatible string for it.

Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
---
 Documentation/devicetree/bindings/spi/spi-sun6i.txt | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/spi/spi-sun6i.txt b/Documentation/devicetree/bindings/spi/spi-sun6i.txt
index 435a8e0..33f490f 100644
--- a/Documentation/devicetree/bindings/spi/spi-sun6i.txt
+++ b/Documentation/devicetree/bindings/spi/spi-sun6i.txt
@@ -1,7 +1,10 @@
 Allwinner A31/H3 SPI controller
 
 Required properties:
-- compatible: Should be "allwinner,sun6i-a31-spi" or "allwinner,sun8i-h3-spi".
+- compatible: should be:
+	- "allwinner,sun6i-a31-spi"
+	- "allwinner,sun8i-h3-spi"
+	- "allwinner,suniv-f1c100s-spi", "allwinner,sun8i-h3-spi"
 - reg: Should contain register location and length.
 - interrupts: Should contain interrupt.
 - clocks: phandle to the clocks feeding the SPI controller. Two are
-- 
2.7.4


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[PATCH 5/7] ARM: dts: suniv: Add SPI device-tree nodes

[Mesih Kilinc]

Allwinner suniv F1C100s has similar SPI controller as sun8i H3.
F1C100s has no dedicated mod clock, instead it uses AHB bus clock.

Add support for both SPI0 and SPI1.

Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
---
 arch/arm/boot/dts/suniv-f1c100s.dtsi | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
index 953228c..1b332d9 100644
--- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
+++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
@@ -143,5 +143,31 @@
 			resets = <&ccu RST_BUS_UART2>;
 			status = "disabled";
 		};
+
+		spi0: spi@1c05000 {
+			compatible = "allwinner,suniv-f1c100s-spi",
+				     "allwinner,sun8i-h3-spi";
+			reg = <0x01c05000 0x1000>;
+			interrupts = <10>;
+			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_BUS_SPI0>;
+			clock-names = "ahb", "mod";
+			resets = <&ccu RST_BUS_SPI0>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		spi1: spi@1c06000 {
+			compatible = "allwinner,suniv-f1c100s-spi",
+				     "allwinner,sun8i-h3-spi";
+			reg = <0x01c06000 0x1000>;
+			interrupts = <11>;
+			clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_BUS_SPI1>;
+			clock-names = "ahb", "mod";
+			resets = <&ccu RST_BUS_SPI1>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
 	};
 };
-- 
2.7.4

[PATCH 5/7] ARM: dts: suniv: Add SPI device-tree nodes

[Mesih Kilinc]

Allwinner suniv F1C100s has similar SPI controller as sun8i H3.
F1C100s has no dedicated mod clock, instead it uses AHB bus clock.

Add support for both SPI0 and SPI1.

Signed-off-by: Mesih Kilinc <mesihkilinc-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 arch/arm/boot/dts/suniv-f1c100s.dtsi | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
index 953228c..1b332d9 100644
--- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
+++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
@@ -143,5 +143,31 @@
 			resets = <&ccu RST_BUS_UART2>;
 			status = "disabled";
 		};
+
+		spi0: spi@1c05000 {
+			compatible = "allwinner,suniv-f1c100s-spi",
+				     "allwinner,sun8i-h3-spi";
+			reg = <0x01c05000 0x1000>;
+			interrupts = <10>;
+			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_BUS_SPI0>;
+			clock-names = "ahb", "mod";
+			resets = <&ccu RST_BUS_SPI0>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		spi1: spi@1c06000 {
+			compatible = "allwinner,suniv-f1c100s-spi",
+				     "allwinner,sun8i-h3-spi";
+			reg = <0x01c06000 0x1000>;
+			interrupts = <11>;
+			clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_BUS_SPI1>;
+			clock-names = "ahb", "mod";
+			resets = <&ccu RST_BUS_SPI1>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
 	};
 };
-- 
2.7.4

[PATCH 5/7] ARM: dts: suniv: Add SPI device-tree nodes

[Mesih Kilinc]

Allwinner suniv F1C100s has similar SPI controller as sun8i H3.
F1C100s has no dedicated mod clock, instead it uses AHB bus clock.

Add support for both SPI0 and SPI1.

Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
---
 arch/arm/boot/dts/suniv-f1c100s.dtsi | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
index 953228c..1b332d9 100644
--- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
+++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
@@ -143,5 +143,31 @@
 			resets = <&ccu RST_BUS_UART2>;
 			status = "disabled";
 		};
+
+		spi0: spi@1c05000 {
+			compatible = "allwinner,suniv-f1c100s-spi",
+				     "allwinner,sun8i-h3-spi";
+			reg = <0x01c05000 0x1000>;
+			interrupts = <10>;
+			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_BUS_SPI0>;
+			clock-names = "ahb", "mod";
+			resets = <&ccu RST_BUS_SPI0>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		spi1: spi@1c06000 {
+			compatible = "allwinner,suniv-f1c100s-spi",
+				     "allwinner,sun8i-h3-spi";
+			reg = <0x01c06000 0x1000>;
+			interrupts = <11>;
+			clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_BUS_SPI1>;
+			clock-names = "ahb", "mod";
+			resets = <&ccu RST_BUS_SPI1>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
 	};
 };
-- 
2.7.4


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[PATCH 6/7] ARM: dts: suniv: Add pinmux for SPI0 and SPI1 of F1C100s

[Mesih Kilinc]

PC0~PC4 is pin group for SPI0. PA0~PA4 is pin group for SPI1.
Add device tree nodes for this groups.

Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
---
 arch/arm/boot/dts/suniv-f1c100s.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
index 1b332d9..a92a411 100644
--- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
+++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
@@ -96,6 +96,16 @@
 				pins = "PE0", "PE1";
 				function = "uart0";
 			};
+
+			spi0_pc_pins: spi0-pc-pins {
+				pins = "PC0", "PC1", "PC2", "PC3";
+				function = "spi0";
+			};
+
+			spi1_pa_pins: spi1-pa-pins {
+				pins = "PA0", "PA1", "PA2", "PA3";
+				function = "spi1";
+			};
 		};
 
 		timer@1c20c00 {
-- 
2.7.4

[PATCH 6/7] ARM: dts: suniv: Add pinmux for SPI0 and SPI1 of F1C100s

[Mesih Kilinc]

PC0~PC4 is pin group for SPI0. PA0~PA4 is pin group for SPI1.
Add device tree nodes for this groups.

Signed-off-by: Mesih Kilinc <mesihkilinc-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 arch/arm/boot/dts/suniv-f1c100s.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
index 1b332d9..a92a411 100644
--- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
+++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
@@ -96,6 +96,16 @@
 				pins = "PE0", "PE1";
 				function = "uart0";
 			};
+
+			spi0_pc_pins: spi0-pc-pins {
+				pins = "PC0", "PC1", "PC2", "PC3";
+				function = "spi0";
+			};
+
+			spi1_pa_pins: spi1-pa-pins {
+				pins = "PA0", "PA1", "PA2", "PA3";
+				function = "spi1";
+			};
 		};
 
 		timer@1c20c00 {
-- 
2.7.4

[PATCH 6/7] ARM: dts: suniv: Add pinmux for SPI0 and SPI1 of F1C100s

[Mesih Kilinc]

PC0~PC4 is pin group for SPI0. PA0~PA4 is pin group for SPI1.
Add device tree nodes for this groups.

Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
---
 arch/arm/boot/dts/suniv-f1c100s.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
index 1b332d9..a92a411 100644
--- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
+++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
@@ -96,6 +96,16 @@
 				pins = "PE0", "PE1";
 				function = "uart0";
 			};
+
+			spi0_pc_pins: spi0-pc-pins {
+				pins = "PC0", "PC1", "PC2", "PC3";
+				function = "spi0";
+			};
+
+			spi1_pa_pins: spi1-pa-pins {
+				pins = "PA0", "PA1", "PA2", "PA3";
+				function = "spi1";
+			};
 		};
 
 		timer@1c20c00 {
-- 
2.7.4


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[PATCH 7/7] ARM: dts: f1c100s: Activate SPI flash on Lichee Pi Nano

[Mesih Kilinc]

The Lichee Pi Nano board has a Winbond W25Q128FVSIQ 128Mbit SPI NOR flash
connected to the SPI0 controller of F1C100s SoC, via the pinmux group at
PC bank; so it's bootable.

Enable this SPI flash.

Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
---
 arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
index a1154e6..52a29be 100644
--- a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
+++ b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
@@ -24,3 +24,16 @@
 	pinctrl-0 = <&uart0_pe_pins>;
 	status = "okay";
 };
+
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0_pc_pins>;
+	status = "okay";
+	flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "winbond,w25q128", "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <50000000>;
+	};
+};
-- 
2.7.4

[PATCH 7/7] ARM: dts: f1c100s: Activate SPI flash on Lichee Pi Nano

[Mesih Kilinc]

The Lichee Pi Nano board has a Winbond W25Q128FVSIQ 128Mbit SPI NOR flash
connected to the SPI0 controller of F1C100s SoC, via the pinmux group at
PC bank; so it's bootable.

Enable this SPI flash.

Signed-off-by: Mesih Kilinc <mesihkilinc-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
index a1154e6..52a29be 100644
--- a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
+++ b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
@@ -24,3 +24,16 @@
 	pinctrl-0 = <&uart0_pe_pins>;
 	status = "okay";
 };
+
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0_pc_pins>;
+	status = "okay";
+	flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "winbond,w25q128", "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <50000000>;
+	};
+};
-- 
2.7.4

[PATCH 7/7] ARM: dts: f1c100s: Activate SPI flash on Lichee Pi Nano

[Mesih Kilinc]

The Lichee Pi Nano board has a Winbond W25Q128FVSIQ 128Mbit SPI NOR flash
connected to the SPI0 controller of F1C100s SoC, via the pinmux group at
PC bank; so it's bootable.

Enable this SPI flash.

Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
---
 arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
index a1154e6..52a29be 100644
--- a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
+++ b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
@@ -24,3 +24,16 @@
 	pinctrl-0 = <&uart0_pe_pins>;
 	status = "okay";
 };
+
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0_pc_pins>;
+	status = "okay";
+	flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "winbond,w25q128", "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <50000000>;
+	};
+};
-- 
2.7.4


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Re: [PATCH 6/7] ARM: dts: suniv: Add pinmux for SPI0 and SPI1 of F1C100s

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 1243 bytes --]

On Mon, Feb 11, 2019 at 12:21:12PM +0300, Mesih Kilinc wrote:
> PC0~PC4 is pin group for SPI0. PA0~PA4 is pin group for SPI1.
> Add device tree nodes for this groups.
> 
> Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
> ---
>  arch/arm/boot/dts/suniv-f1c100s.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
> index 1b332d9..a92a411 100644
> --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
> +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
> @@ -96,6 +96,16 @@
>  				pins = "PE0", "PE1";
>  				function = "uart0";
>  			};
> +
> +			spi0_pc_pins: spi0-pc-pins {
> +				pins = "PC0", "PC1", "PC2", "PC3";
> +				function = "spi0";
> +			};
> +
> +			spi1_pa_pins: spi1-pa-pins {
> +				pins = "PA0", "PA1", "PA2", "PA3";
> +				function = "spi1";
> +			};

Are they the only options for the muxing of the SPI pins? if so, you'd
need to remove the pin bank, and to set the pinctrl-0 and
pinctrl-names in the DTSI.

We also move the CS pin out in a separate group to accomodate devices
that use a GPIO instead.

Maxime

-- 
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

[-- Attachment #2: signature.asc --]
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Re: [PATCH 6/7] ARM: dts: suniv: Add pinmux for SPI0 and SPI1 of F1C100s

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 1231 bytes --]

On Mon, Feb 11, 2019 at 12:21:12PM +0300, Mesih Kilinc wrote:
> PC0~PC4 is pin group for SPI0. PA0~PA4 is pin group for SPI1.
> Add device tree nodes for this groups.
> 
> Signed-off-by: Mesih Kilinc <mesihkilinc-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
>  arch/arm/boot/dts/suniv-f1c100s.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
> index 1b332d9..a92a411 100644
> --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
> +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
> @@ -96,6 +96,16 @@
>  				pins = "PE0", "PE1";
>  				function = "uart0";
>  			};
> +
> +			spi0_pc_pins: spi0-pc-pins {
> +				pins = "PC0", "PC1", "PC2", "PC3";
> +				function = "spi0";
> +			};
> +
> +			spi1_pa_pins: spi1-pa-pins {
> +				pins = "PA0", "PA1", "PA2", "PA3";
> +				function = "spi1";
> +			};

Are they the only options for the muxing of the SPI pins? if so, you'd
need to remove the pin bank, and to set the pinctrl-0 and
pinctrl-names in the DTSI.

We also move the CS pin out in a separate group to accomodate devices
that use a GPIO instead.

Maxime

-- 
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

Re: [PATCH 6/7] ARM: dts: suniv: Add pinmux for SPI0 and SPI1 of F1C100s

[Maxime Ripard]

[-- Attachment #1.1: Type: text/plain, Size: 1243 bytes --]

On Mon, Feb 11, 2019 at 12:21:12PM +0300, Mesih Kilinc wrote:
> PC0~PC4 is pin group for SPI0. PA0~PA4 is pin group for SPI1.
> Add device tree nodes for this groups.
> 
> Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
> ---
>  arch/arm/boot/dts/suniv-f1c100s.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
> index 1b332d9..a92a411 100644
> --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
> +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
> @@ -96,6 +96,16 @@
>  				pins = "PE0", "PE1";
>  				function = "uart0";
>  			};
> +
> +			spi0_pc_pins: spi0-pc-pins {
> +				pins = "PC0", "PC1", "PC2", "PC3";
> +				function = "spi0";
> +			};
> +
> +			spi1_pa_pins: spi1-pa-pins {
> +				pins = "PA0", "PA1", "PA2", "PA3";
> +				function = "spi1";
> +			};

Are they the only options for the muxing of the SPI pins? if so, you'd
need to remove the pin bank, and to set the pinctrl-0 and
pinctrl-names in the DTSI.

We also move the CS pin out in a separate group to accomodate devices
that use a GPIO instead.

Maxime

-- 
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

[-- Attachment #2: Type: text/plain, Size: 176 bytes --]

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Re: [PATCH 4/7] dt-bindings: spi: Add Support for Allwinner F1C100s

[Rob Herring]

On Mon, 11 Feb 2019 12:21:10 +0300, Mesih Kilinc wrote:
> Allwinner suniv F1C100s has similar SPI controllers as sun8i H3.
> Add compatible string for it.
> 
> Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
> ---
>  Documentation/devicetree/bindings/spi/spi-sun6i.txt | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

Re: [PATCH 4/7] dt-bindings: spi: Add Support for Allwinner F1C100s

[Rob Herring]

On Mon, 11 Feb 2019 12:21:10 +0300, Mesih Kilinc wrote:
> Allwinner suniv F1C100s has similar SPI controllers as sun8i H3.
> Add compatible string for it.
> 
> Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
> ---
>  Documentation/devicetree/bindings/spi/spi-sun6i.txt | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

Re: [PATCH 4/7] dt-bindings: spi: Add Support for Allwinner F1C100s

[Rob Herring]

On Mon, 11 Feb 2019 12:21:10 +0300, Mesih Kilinc wrote:
> Allwinner suniv F1C100s has similar SPI controllers as sun8i H3.
> Add compatible string for it.
> 
> Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
> ---
>  Documentation/devicetree/bindings/spi/spi-sun6i.txt | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

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Re: [PATCH 0/7] Timer & SPI support for Allwinner suniv F1C100s

[Icenowy Zheng]

在 2019-02-11一的 12:21 +0300，Mesih Kilinc写道：
> This is followup series for F1C100s initial support patchset. 
> All patches merged except patch 1 ~ 2 which is related to timer.
> I am resending those since they are already have Acked tags.

Ping.

Could you please merge these timer-related patches?

Thanks!
Icenowy

> 
> Our dt-bindings for F1C100s are merged, we can now use them at our 
> device tree source - patch 3.
> 
> Also this series add spi support and enables spi flash at Lichee-pi
> Nano
> in patch 4 ~ 7. This patches are based on Icenowy's work.
> 
> Thanks!
> 
> Mesih Kilinc (7):
>   dt-bindings: timer: Add Allwinner suniv timer
>   clocksource: sun4i: add a compatible for suniv
>   ARM: dts: suniv: Add dt-binding headers for F1C100s
>   dt-bindings: spi: Add Support for Allwinner F1C100s
>   ARM: dts: suniv: Add SPI device-tree nodes
>   ARM: dts: suniv: Add pinmux for SPI0 and SPI1 of F1C100s
>   ARM: dts: f1c100s: Activate SPI flash on Lichee Pi Nano
> 
>  .../devicetree/bindings/spi/spi-sun6i.txt          |  5 +-
>  .../bindings/timer/allwinner,sun4i-timer.txt       |  4 +-
>  arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts  | 13 ++++++
>  arch/arm/boot/dts/suniv-f1c100s.dtsi               | 53
> +++++++++++++++++++---
>  drivers/clocksource/timer-sun4i.c                  |  5 +-
>  5 files changed, 70 insertions(+), 10 deletions(-)
> 

Re: [PATCH 0/7] Timer & SPI support for Allwinner suniv F1C100s

[Icenowy Zheng]

在 2019-02-11一的 12:21 +0300，Mesih Kilinc写道：
> This is followup series for F1C100s initial support patchset. 
> All patches merged except patch 1 ~ 2 which is related to timer.
> I am resending those since they are already have Acked tags.

Ping.

Could you please merge these timer-related patches?

Thanks!
Icenowy

> 
> Our dt-bindings for F1C100s are merged, we can now use them at our 
> device tree source - patch 3.
> 
> Also this series add spi support and enables spi flash at Lichee-pi
> Nano
> in patch 4 ~ 7. This patches are based on Icenowy's work.
> 
> Thanks!
> 
> Mesih Kilinc (7):
>   dt-bindings: timer: Add Allwinner suniv timer
>   clocksource: sun4i: add a compatible for suniv
>   ARM: dts: suniv: Add dt-binding headers for F1C100s
>   dt-bindings: spi: Add Support for Allwinner F1C100s
>   ARM: dts: suniv: Add SPI device-tree nodes
>   ARM: dts: suniv: Add pinmux for SPI0 and SPI1 of F1C100s
>   ARM: dts: f1c100s: Activate SPI flash on Lichee Pi Nano
> 
>  .../devicetree/bindings/spi/spi-sun6i.txt          |  5 +-
>  .../bindings/timer/allwinner,sun4i-timer.txt       |  4 +-
>  arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts  | 13 ++++++
>  arch/arm/boot/dts/suniv-f1c100s.dtsi               | 53
> +++++++++++++++++++---
>  drivers/clocksource/timer-sun4i.c                  |  5 +-
>  5 files changed, 70 insertions(+), 10 deletions(-)
> 


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Re: [PATCH 0/7] Timer & SPI support for Allwinner suniv F1C100s

[Icenowy Zheng]

在 2019-02-11一的 12:21 +0300，Mesih Kilinc写道：
> This is followup series for F1C100s initial support patchset. 
> All patches merged except patch 1 ~ 2 which is related to timer.
> I am resending those since they are already have Acked tags.

Ping.

Could you please merge these timer-related patches?

Thanks!
Icenowy

> 
> Our dt-bindings for F1C100s are merged, we can now use them at our 
> device tree source - patch 3.
> 
> Also this series add spi support and enables spi flash at Lichee-pi
> Nano
> in patch 4 ~ 7. This patches are based on Icenowy's work.
> 
> Thanks!
> 
> Mesih Kilinc (7):
>   dt-bindings: timer: Add Allwinner suniv timer
>   clocksource: sun4i: add a compatible for suniv
>   ARM: dts: suniv: Add dt-binding headers for F1C100s
>   dt-bindings: spi: Add Support for Allwinner F1C100s
>   ARM: dts: suniv: Add SPI device-tree nodes
>   ARM: dts: suniv: Add pinmux for SPI0 and SPI1 of F1C100s
>   ARM: dts: f1c100s: Activate SPI flash on Lichee Pi Nano
> 
>  .../devicetree/bindings/spi/spi-sun6i.txt          |  5 +-
>  .../bindings/timer/allwinner,sun4i-timer.txt       |  4 +-
>  arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts  | 13 ++++++
>  arch/arm/boot/dts/suniv-f1c100s.dtsi               | 53
> +++++++++++++++++++---
>  drivers/clocksource/timer-sun4i.c                  |  5 +-
>  5 files changed, 70 insertions(+), 10 deletions(-)
> 


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Re: [PATCH 0/7] Timer & SPI support for Allwinner suniv F1C100s

[Daniel Lezcano]

On 17/03/2019 18:39, Icenowy Zheng wrote:
> 在 2019-02-11一的 12:21 +0300，Mesih Kilinc写道：
>> This is followup series for F1C100s initial support patchset. 
>> All patches merged except patch 1 ~ 2 which is related to timer.
>> I am resending those since they are already have Acked tags.
> 
> Ping.
> 
> Could you please merge these timer-related patches?

Hi,

I acked the timer-related patches. If you resend the patches with my
acked-by I will consider them to go through the allwinner tree.

Do you want me to take 1 and 2 through my tree?



>> Our dt-bindings for F1C100s are merged, we can now use them at our 
>> device tree source - patch 3.
>>
>> Also this series add spi support and enables spi flash at Lichee-pi
>> Nano
>> in patch 4 ~ 7. This patches are based on Icenowy's work.
>>
>> Thanks!
>>
>> Mesih Kilinc (7):
>>   dt-bindings: timer: Add Allwinner suniv timer
>>   clocksource: sun4i: add a compatible for suniv
>>   ARM: dts: suniv: Add dt-binding headers for F1C100s
>>   dt-bindings: spi: Add Support for Allwinner F1C100s
>>   ARM: dts: suniv: Add SPI device-tree nodes
>>   ARM: dts: suniv: Add pinmux for SPI0 and SPI1 of F1C100s
>>   ARM: dts: f1c100s: Activate SPI flash on Lichee Pi Nano
>>
>>  .../devicetree/bindings/spi/spi-sun6i.txt          |  5 +-
>>  .../bindings/timer/allwinner,sun4i-timer.txt       |  4 +-
>>  arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts  | 13 ++++++
>>  arch/arm/boot/dts/suniv-f1c100s.dtsi               | 53
>> +++++++++++++++++++---
>>  drivers/clocksource/timer-sun4i.c                  |  5 +-
>>  5 files changed, 70 insertions(+), 10 deletions(-)
>>
> 


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Re: [PATCH 0/7] Timer & SPI support for Allwinner suniv F1C100s

[Daniel Lezcano]

On 17/03/2019 18:39, Icenowy Zheng wrote:
> 在 2019-02-11一的 12:21 +0300，Mesih Kilinc写道：
>> This is followup series for F1C100s initial support patchset. 
>> All patches merged except patch 1 ~ 2 which is related to timer.
>> I am resending those since they are already have Acked tags.
> 
> Ping.
> 
> Could you please merge these timer-related patches?

Hi,

I acked the timer-related patches. If you resend the patches with my
acked-by I will consider them to go through the allwinner tree.

Do you want me to take 1 and 2 through my tree?



>> Our dt-bindings for F1C100s are merged, we can now use them at our 
>> device tree source - patch 3.
>>
>> Also this series add spi support and enables spi flash at Lichee-pi
>> Nano
>> in patch 4 ~ 7. This patches are based on Icenowy's work.
>>
>> Thanks!
>>
>> Mesih Kilinc (7):
>>   dt-bindings: timer: Add Allwinner suniv timer
>>   clocksource: sun4i: add a compatible for suniv
>>   ARM: dts: suniv: Add dt-binding headers for F1C100s
>>   dt-bindings: spi: Add Support for Allwinner F1C100s
>>   ARM: dts: suniv: Add SPI device-tree nodes
>>   ARM: dts: suniv: Add pinmux for SPI0 and SPI1 of F1C100s
>>   ARM: dts: f1c100s: Activate SPI flash on Lichee Pi Nano
>>
>>  .../devicetree/bindings/spi/spi-sun6i.txt          |  5 +-
>>  .../bindings/timer/allwinner,sun4i-timer.txt       |  4 +-
>>  arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts  | 13 ++++++
>>  arch/arm/boot/dts/suniv-f1c100s.dtsi               | 53
>> +++++++++++++++++++---
>>  drivers/clocksource/timer-sun4i.c                  |  5 +-
>>  5 files changed, 70 insertions(+), 10 deletions(-)
>>
> 


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Re: [PATCH 0/7] Timer & SPI support for Allwinner suniv F1C100s

[Daniel Lezcano]

On 17/03/2019 18:39, Icenowy Zheng wrote:
> 在 2019-02-11一的 12:21 +0300，Mesih Kilinc写道：
>> This is followup series for F1C100s initial support patchset. 
>> All patches merged except patch 1 ~ 2 which is related to timer.
>> I am resending those since they are already have Acked tags.
> 
> Ping.
> 
> Could you please merge these timer-related patches?

Hi,

I acked the timer-related patches. If you resend the patches with my
acked-by I will consider them to go through the allwinner tree.

Do you want me to take 1 and 2 through my tree?



>> Our dt-bindings for F1C100s are merged, we can now use them at our 
>> device tree source - patch 3.
>>
>> Also this series add spi support and enables spi flash at Lichee-pi
>> Nano
>> in patch 4 ~ 7. This patches are based on Icenowy's work.
>>
>> Thanks!
>>
>> Mesih Kilinc (7):
>>   dt-bindings: timer: Add Allwinner suniv timer
>>   clocksource: sun4i: add a compatible for suniv
>>   ARM: dts: suniv: Add dt-binding headers for F1C100s
>>   dt-bindings: spi: Add Support for Allwinner F1C100s
>>   ARM: dts: suniv: Add SPI device-tree nodes
>>   ARM: dts: suniv: Add pinmux for SPI0 and SPI1 of F1C100s
>>   ARM: dts: f1c100s: Activate SPI flash on Lichee Pi Nano
>>
>>  .../devicetree/bindings/spi/spi-sun6i.txt          |  5 +-
>>  .../bindings/timer/allwinner,sun4i-timer.txt       |  4 +-
>>  arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts  | 13 ++++++
>>  arch/arm/boot/dts/suniv-f1c100s.dtsi               | 53
>> +++++++++++++++++++---
>>  drivers/clocksource/timer-sun4i.c                  |  5 +-
>>  5 files changed, 70 insertions(+), 10 deletions(-)
>>
> 


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Re: [PATCH 0/7] Timer & SPI support for Allwinner suniv F1C100s

[Icenowy Zheng]

在 2019-03-17日的 21:52 +0100，Daniel Lezcano写道：
> On 17/03/2019 18:39, Icenowy Zheng wrote:
> > 在 2019-02-11一的 12:21 +0300，Mesih Kilinc写道：
> > > This is followup series for F1C100s initial support patchset. 
> > > All patches merged except patch 1 ~ 2 which is related to timer.
> > > I am resending those since they are already have Acked tags.
> > 
> > Ping.
> > 
> > Could you please merge these timer-related patches?
> 
> Hi,
> 
> I acked the timer-related patches. If you resend the patches with my
> acked-by I will consider them to go through the allwinner tree.
> 
> Do you want me to take 1 and 2 through my tree?

Please. They also have the ACK from Allwinner/sunXi maintainer.

> 
> 
> 
> > > Our dt-bindings for F1C100s are merged, we can now use them at
> > > our 
> > > device tree source - patch 3.
> > > 
> > > Also this series add spi support and enables spi flash at Lichee-
> > > pi
> > > Nano
> > > in patch 4 ~ 7. This patches are based on Icenowy's work.
> > > 
> > > Thanks!
> > > 
> > > Mesih Kilinc (7):
> > >   dt-bindings: timer: Add Allwinner suniv timer
> > >   clocksource: sun4i: add a compatible for suniv
> > >   ARM: dts: suniv: Add dt-binding headers for F1C100s
> > >   dt-bindings: spi: Add Support for Allwinner F1C100s
> > >   ARM: dts: suniv: Add SPI device-tree nodes
> > >   ARM: dts: suniv: Add pinmux for SPI0 and SPI1 of F1C100s
> > >   ARM: dts: f1c100s: Activate SPI flash on Lichee Pi Nano
> > > 
> > >  .../devicetree/bindings/spi/spi-sun6i.txt          |  5 +-
> > >  .../bindings/timer/allwinner,sun4i-timer.txt       |  4 +-
> > >  arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts  | 13 ++++++
> > >  arch/arm/boot/dts/suniv-f1c100s.dtsi               | 53
> > > +++++++++++++++++++---
> > >  drivers/clocksource/timer-sun4i.c                  |  5 +-
> > >  5 files changed, 70 insertions(+), 10 deletions(-)
> > > 
> 
> 

Re: [PATCH 0/7] Timer & SPI support for Allwinner suniv F1C100s

[Icenowy Zheng]

在 2019-03-17日的 21:52 +0100，Daniel Lezcano写道：
> On 17/03/2019 18:39, Icenowy Zheng wrote:
> > 在 2019-02-11一的 12:21 +0300，Mesih Kilinc写道：
> > > This is followup series for F1C100s initial support patchset. 
> > > All patches merged except patch 1 ~ 2 which is related to timer.
> > > I am resending those since they are already have Acked tags.
> > 
> > Ping.
> > 
> > Could you please merge these timer-related patches?
> 
> Hi,
> 
> I acked the timer-related patches. If you resend the patches with my
> acked-by I will consider them to go through the allwinner tree.
> 
> Do you want me to take 1 and 2 through my tree?

Please. They also have the ACK from Allwinner/sunXi maintainer.

> 
> 
> 
> > > Our dt-bindings for F1C100s are merged, we can now use them at
> > > our 
> > > device tree source - patch 3.
> > > 
> > > Also this series add spi support and enables spi flash at Lichee-
> > > pi
> > > Nano
> > > in patch 4 ~ 7. This patches are based on Icenowy's work.
> > > 
> > > Thanks!
> > > 
> > > Mesih Kilinc (7):
> > >   dt-bindings: timer: Add Allwinner suniv timer
> > >   clocksource: sun4i: add a compatible for suniv
> > >   ARM: dts: suniv: Add dt-binding headers for F1C100s
> > >   dt-bindings: spi: Add Support for Allwinner F1C100s
> > >   ARM: dts: suniv: Add SPI device-tree nodes
> > >   ARM: dts: suniv: Add pinmux for SPI0 and SPI1 of F1C100s
> > >   ARM: dts: f1c100s: Activate SPI flash on Lichee Pi Nano
> > > 
> > >  .../devicetree/bindings/spi/spi-sun6i.txt          |  5 +-
> > >  .../bindings/timer/allwinner,sun4i-timer.txt       |  4 +-
> > >  arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts  | 13 ++++++
> > >  arch/arm/boot/dts/suniv-f1c100s.dtsi               | 53
> > > +++++++++++++++++++---
> > >  drivers/clocksource/timer-sun4i.c                  |  5 +-
> > >  5 files changed, 70 insertions(+), 10 deletions(-)
> > > 
> 
> 


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Re: [PATCH 0/7] Timer & SPI support for Allwinner suniv F1C100s

[Daniel Lezcano]

On 18/03/2019 08:18, Icenowy Zheng wrote:
> 在 2019-03-17日的 21:52 +0100，Daniel Lezcano写道：
>> On 17/03/2019 18:39, Icenowy Zheng wrote:
>>> 在 2019-02-11一的 12:21 +0300，Mesih Kilinc写道：
>>>> This is followup series for F1C100s initial support patchset. 
>>>> All patches merged except patch 1 ~ 2 which is related to timer.
>>>> I am resending those since they are already have Acked tags.
>>>
>>> Ping.
>>>
>>> Could you please merge these timer-related patches?
>>
>> Hi,
>>
>> I acked the timer-related patches. If you resend the patches with my
>> acked-by I will consider them to go through the allwinner tree.
>>
>> Do you want me to take 1 and 2 through my tree?
> 
> Please. They also have the ACK from Allwinner/sunXi maintainer.

Applied for 5.2. Thanks

By the way, I did not find any trace of the email in my mailer, was I
To'ed or CC'ed for those patches ?


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Re: [PATCH 0/7] Timer & SPI support for Allwinner suniv F1C100s

[Daniel Lezcano]

On 18/03/2019 08:18, Icenowy Zheng wrote:
> 在 2019-03-17日的 21:52 +0100，Daniel Lezcano写道：
>> On 17/03/2019 18:39, Icenowy Zheng wrote:
>>> 在 2019-02-11一的 12:21 +0300，Mesih Kilinc写道：
>>>> This is followup series for F1C100s initial support patchset. 
>>>> All patches merged except patch 1 ~ 2 which is related to timer.
>>>> I am resending those since they are already have Acked tags.
>>>
>>> Ping.
>>>
>>> Could you please merge these timer-related patches?
>>
>> Hi,
>>
>> I acked the timer-related patches. If you resend the patches with my
>> acked-by I will consider them to go through the allwinner tree.
>>
>> Do you want me to take 1 and 2 through my tree?
> 
> Please. They also have the ACK from Allwinner/sunXi maintainer.

Applied for 5.2. Thanks

By the way, I did not find any trace of the email in my mailer, was I
To'ed or CC'ed for those patches ?


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Re: [PATCH 0/7] Timer & SPI support for Allwinner suniv F1C100s

[Mesih Kılınç]

[-- Attachment #1: Type: text/plain, Size: 1709 bytes --]

Yep, it's my fault. Sorry about that.

18 Mar 2019 Pzt 11:04 tarihinde Daniel Lezcano <daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
şunu yazdı:

> On 18/03/2019 08:18, Icenowy Zheng wrote:
> > 在 2019-03-17日的 21:52 +0100，Daniel Lezcano写道：
> >> On 17/03/2019 18:39, Icenowy Zheng wrote:
> >>> 在 2019-02-11一的 12:21 +0300，Mesih Kilinc写道：
> >>>> This is followup series for F1C100s initial support patchset.
> >>>> All patches merged except patch 1 ~ 2 which is related to timer.
> >>>> I am resending those since they are already have Acked tags.
> >>>
> >>> Ping.
> >>>
> >>> Could you please merge these timer-related patches?
> >>
> >> Hi,
> >>
> >> I acked the timer-related patches. If you resend the patches with my
> >> acked-by I will consider them to go through the allwinner tree.
> >>
> >> Do you want me to take 1 and 2 through my tree?
> >
> > Please. They also have the ACK from Allwinner/sunXi maintainer.
>
> Applied for 5.2. Thanks
>
> By the way, I did not find any trace of the email in my mailer, was I
> To'ed or CC'ed for those patches ?
>
>
> --
>  <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
>
> Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
> <http://twitter.com/#!/linaroorg> Twitter |
> <http://www.linaro.org/linaro-blog/> Blog
>
>

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