From: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
To: Rob Herring <robh@kernel.org>
Cc: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Linus Walleij <linus.walleij@linaro.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
"open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@vger.kernel.org>, LKML <linux-kernel@vger.kernel.org>,
Biju Das <biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH] dt-bindings: pinctrl: renesas: Document RZ/Five SoC
Date: Fri, 12 Aug 2022 09:35:20 +0100 [thread overview]
Message-ID: <CA+V-a8smt5Z+Ksa4u5-_EFo7jofneh8udFFLHNBV4Qp0C2vevw@mail.gmail.com> (raw)
In-Reply-To: <20220727154016.GA2719108-robh@kernel.org>
Hi Rob,
Thank you for the review.
On Wed, Jul 27, 2022 at 4:40 PM Rob Herring <robh@kernel.org> wrote:
>
> On Tue, Jul 26, 2022 at 06:53:15PM +0100, Lad Prabhakar wrote:
> > RZ/Five SoC is pin compatible with RZ/G2UL (Type 1) SoC. This patch
> > updates the comment to include RZ/Five SoC so that we make it clear
> > "renesas,r9a07g043-pinctrl" compatible string will be used for RZ/Five
> > SoC.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > .../devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
>
> Same comments as here[1].
>
This block is identical on RZ/G2UL and RZ/Five SoC.
> Rob
>
> [1] https://lore.kernel.org/all/20220727153738.GA2696116-robh@kernel.org/
Cheers,
Prabhakar
next prev parent reply other threads:[~2022-08-12 8:35 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-26 17:53 [PATCH] dt-bindings: pinctrl: renesas: Document RZ/Five SoC Lad Prabhakar
2022-07-27 15:40 ` Rob Herring
2022-08-12 8:35 ` Lad, Prabhakar [this message]
2022-08-12 9:08 ` Geert Uytterhoeven
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