Hi Wolfram,

On Sun, May 17, 2020 at 10:08 PM Wolfram Sang <wsa@the-dreams.de> wrote:
>
> On Fri, May 15, 2020 at 04:08:57PM +0100, Lad Prabhakar wrote:
> > Add a device node for the Watchdog Timer (RWDT) controller on the Renesas
> > RZ/G1H (r8a7742) SoC.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
>
> The DTS change looks fine, I checked it against similar SoCs (like the
> previous patched). So, for that:
>
> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
>
Thank you for review.

> However, just to make sure, have you checked the WDT (especially reboot)
> with SMP and multiple CPU cores enabled? Some early Gen2 SoCs had issues
> there.
>
Its similar to as seen on Rcar-H2 where just the A15 cores are up and
A7 cores fail to boot. Attached is the boot log where reboot works as
expected with all A15 core up. Although I have tested the internal
release based on 3.10 where all the cores are up which used bootarg
apmu=multicluster (https://patchwork.kernel.org/patch/3948791/). So
there is some work involved to get all the A7's up and running.


Cheers,
--Prabhakar