From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 838B0C25B06 for ; Thu, 11 Aug 2022 23:38:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236686AbiHKXiP (ORCPT ); Thu, 11 Aug 2022 19:38:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39890 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233974AbiHKXiM (ORCPT ); Thu, 11 Aug 2022 19:38:12 -0400 Received: from mail-yw1-x1132.google.com (mail-yw1-x1132.google.com [IPv6:2607:f8b0:4864:20::1132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8CF4D9AFC4; Thu, 11 Aug 2022 16:38:10 -0700 (PDT) Received: by mail-yw1-x1132.google.com with SMTP id 00721157ae682-32a09b909f6so83809797b3.0; Thu, 11 Aug 2022 16:38:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc; bh=IVeJqcWhysLWzgWUShSqLwDczoSExRUDYbSpzRpTiXQ=; b=k9jTdTI8sjO6UKOTeC4As0uQK2prWT7dSWXk4grIFRnvMm8jpC71fdZnFr5SVlFie3 J5u9uJmgcQOpJlmDc+TH8w1teZWNMP2cwYNXmIFamQ+6Oez/W8vAph4I54W5OMxOaWi3 nzH8r7JhnuooVcrrlRzGUgyXwBWg/NRqQooBGrXsRw4UH8M3qym/5q98FZ1LWi/Q8gIy /zQtmgyn6JIhmp/XPWJ4Df1VyBMTp6GMv1xc22OfjJDwRgldahF+FV3/Co5okfwaU45w TNz2pQ/MqF4vgbz7VCz+TSEj0hjfhtVk2wGEkuFhFUsNc94jgGEMz6GSwyK20nFeGtll uO2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc; bh=IVeJqcWhysLWzgWUShSqLwDczoSExRUDYbSpzRpTiXQ=; b=gas/YV0oWSwcjhLxplnZRCNameIjEGZRHbh57AuBnCY8I0ijJKbv/RpXom7HfSDIyo 920ZEE6PtzIfmiuaqRsHTiXxKZPQ5XALsC77U7gHdvTomdOcEK+P6YfodmYfzxfnmXT4 1xbmcBYtsHIfDoC0kOPD8/YuZWp5PN3ql4clLSy+i5tHUROecBweacjG5nZU63D2yIUH H8jLuH8OSJia6t65GjnEg3yX1WoAXhZOAAoA1oTdxRjzZ58g36mC6kksjRyAagQv33gR 25DPXqNYMcehQNwSFYgPgI9iDFrcE3OhVjfhgGGo47j4qfH9gLGlN0CISpoLVkcqcUp0 dqTQ== X-Gm-Message-State: ACgBeo3b4BtVxtqg84hcf2GT9i/46ElBPBUkrIfSe4qmKvA3Knlakda6 PgYkuN1/5damsl3APcB1M8ha4R35N2Zcf9iGjoaoizT3kro= X-Google-Smtp-Source: AA6agR53mPvsRpuEkAtKI6C+nhnmHsWN+IupElYcWWe4XANRE7IWo58pKjOW1TMETFZly0nVg2UElycZ1NeUGtGGebc= X-Received: by 2002:a0d:f282:0:b0:329:7da1:90e8 with SMTP id b124-20020a0df282000000b003297da190e8mr1535254ywf.519.1660261089750; Thu, 11 Aug 2022 16:38:09 -0700 (PDT) MIME-Version: 1.0 References: <20220726180623.1668-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20220726180623.1668-2-prabhakar.mahadev-lad.rj@bp.renesas.com> <952a85ec-d1e9-7c14-6404-bc087723252f@linaro.org> <3e3c0c80-48eb-098d-977d-a1801036fc0c@linaro.org> In-Reply-To: From: "Lad, Prabhakar" Date: Fri, 12 Aug 2022 00:37:42 +0100 Message-ID: Subject: Re: [PATCH 1/6] dt-bindings: arm: renesas: Ignore the schema for RISC-V arch To: Geert Uytterhoeven Cc: Krzysztof Kozlowski , Lad Prabhakar , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Linux-Renesas , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , linux-riscv , LKML , Biju Das Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Geert, On Thu, Aug 11, 2022 at 4:26 PM Geert Uytterhoeven wrote: > > Hi Prabhakar, > > On Wed, Jul 27, 2022 at 11:48 AM Lad, Prabhakar > wrote: > > On Wed, Jul 27, 2022 at 10:31 AM Krzysztof Kozlowski > > wrote: > > > On 27/07/2022 11:00, Lad, Prabhakar wrote: > > > > On Wed, Jul 27, 2022 at 9:53 AM Krzysztof Kozlowski > > > > wrote: > > > >> On 26/07/2022 20:06, Lad Prabhakar wrote: > > > >>> Ignore the ARM renesas.yaml schema if the board is RZ/Five SMARC EVK > > > >>> (RISC-V arch). > > > >>> > > > >>> Signed-off-by: Lad Prabhakar > > > >>> --- > > > >>> Documentation/devicetree/bindings/arm/renesas.yaml | 9 +++++++++ > > > >>> 1 file changed, 9 insertions(+) > > > >>> > > > >>> diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml > > > >>> index ff80152f092f..f646df1a23af 100644 > > > >>> --- a/Documentation/devicetree/bindings/arm/renesas.yaml > > > >>> +++ b/Documentation/devicetree/bindings/arm/renesas.yaml > > > >>> @@ -9,6 +9,15 @@ title: Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings > > > >>> maintainers: > > > >>> - Geert Uytterhoeven > > > >>> > > > >>> +# We want to ignore this schema if the board is of RISC-V arch > > > >>> +select: > > > >>> + not: > > > >>> + properties: > > > >>> + compatible: > > > >>> + contains: > > > >>> + items: > > > >>> + - const: renesas,r9a07g043f01 > > > >> > > > >> Second issue - why not renesas,r9a07g043? > > > >> > > > > We have two R9A07G043 SOC'S one is based on ARM64 and other on RISC-V. > > > > > > > > RZ/G2UL ARM64: > > > > Type-1 Part Number: R9A07G043U11GBG#BC0 > > > > Type-2 Part Number: R9A07G043U12GBG#BC0 > > > > > > > > RZ/Five RISCV: > > > > 13 x 13 mm Package Part Number: R9A07G043F01GBG#BC0 > > > > > > > > So to differentiate in ARM schema I am using renesas,r9a07g043f01. > > > > > > What is the point to keep then r9a07g043 fallback? The two SoCs are not > > > compatible at all, so they must not use the same fallback. > > > > > Agreed, I wanted to keep it consistent with what was done with ARM64 > > (since both the SoCs shared R9A07G043 part number). > > > > Geert - What are your thoughts on the above? > > "renesas,r9a07g043" is the CPU-less SoC base containing I/O devices. > "renesas,r9a07g043f01", "renesas,r9a07g043u11", and > "renesas,r9a07g043u12" are SoCs built by integrating one or more > RV64 or ARM64 CPU cores and the related interrupt controllers with > the CPU-less SoC base. > That's bang on! which I missed to convenience the DT maintainers. Cheers, Prabhakar From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 50C16C25B06 for ; Thu, 11 Aug 2022 23:38:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:Subject:Message-ID:Date:From: In-Reply-To:References:MIME-Version:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=SjBDJ4yZxYKx4fm+HhHbJ84u6u4gE6vadB7+kQX7y1w=; b=AckjKVI/8fS4oi dhvxoBG24wFoytvv3E9+LrWeUm7H/8IgOozg4WV3OGXvxRpkMyEyjFTASLeaRcEUSZroGzc+9Y/vJ ldGwi+T/ymzsdlqDopB9o0ijwjeUH2AkjUdBK6PD6fj8sti3Y25RsltjiRDwyDws/pLHRxphpMLY6 cwSREqK4+1aKHZZDpPyKB4gdUvFYOQGG+PhqiHxJnhim+v5j6x+NvADfoGaKAYRB/4yNsM1DINdM6 5jDpyo9gUKZaxNaHN+Cfa0IAvS1hUV+Y74x+AMBPTLhH0IRidbrzUCDTPDEqf7AWb6iHt5lh/J9D8 kkjjPUb1UpwgutoYTZ7Q==; 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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc; bh=IVeJqcWhysLWzgWUShSqLwDczoSExRUDYbSpzRpTiXQ=; b=XNsZo0NlTMhha33UfBmts0GwLsOlquYX4ikSiQboXmdGcgcuY1YWydtCw6f9iKKADW XKMn/EDiEomcvTIqk9jsMzZJZo2i/FInU45SS4NXtbkZU78pj79jK0B/HlqLrMx9Urz3 uC/t7OMWg+FJoiurihxsou0SD/6uNQVeKQx1G7VlV3m7jarguaAmRpzuQ6FHP+ybeiJj FWYCL2ASynhNEH58E6+vs/dxEpiKr3oBArkBFsBLjZaqgrOmwlQfovO5o6fmPaAIcyrb A9Xraxhs0QYP7vP0zXf0FfGutsKynsfKWws7p3E4Kp2a0j4uxFk/2yzIr3aItE7Zp4Xq +Y0Q== X-Gm-Message-State: ACgBeo0Vl+68F/R3+7t/f4yvYYLAk99K3aSHy80Te/wxSnL485uDR+zB J1IUHOg0gU/YQl8qk/xV1ddc8NR26FqTo4Sh9p8= X-Google-Smtp-Source: AA6agR53mPvsRpuEkAtKI6C+nhnmHsWN+IupElYcWWe4XANRE7IWo58pKjOW1TMETFZly0nVg2UElycZ1NeUGtGGebc= X-Received: by 2002:a0d:f282:0:b0:329:7da1:90e8 with SMTP id b124-20020a0df282000000b003297da190e8mr1535254ywf.519.1660261089750; Thu, 11 Aug 2022 16:38:09 -0700 (PDT) MIME-Version: 1.0 References: <20220726180623.1668-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20220726180623.1668-2-prabhakar.mahadev-lad.rj@bp.renesas.com> <952a85ec-d1e9-7c14-6404-bc087723252f@linaro.org> <3e3c0c80-48eb-098d-977d-a1801036fc0c@linaro.org> In-Reply-To: From: "Lad, Prabhakar" Date: Fri, 12 Aug 2022 00:37:42 +0100 Message-ID: Subject: Re: [PATCH 1/6] dt-bindings: arm: renesas: Ignore the schema for RISC-V arch To: Geert Uytterhoeven Cc: Krzysztof Kozlowski , Lad Prabhakar , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Linux-Renesas , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , linux-riscv , LKML , Biju Das X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220811_163814_035372_57DC4C8F X-CRM114-Status: GOOD ( 24.21 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Hi Geert, On Thu, Aug 11, 2022 at 4:26 PM Geert Uytterhoeven wrote: > > Hi Prabhakar, > > On Wed, Jul 27, 2022 at 11:48 AM Lad, Prabhakar > wrote: > > On Wed, Jul 27, 2022 at 10:31 AM Krzysztof Kozlowski > > wrote: > > > On 27/07/2022 11:00, Lad, Prabhakar wrote: > > > > On Wed, Jul 27, 2022 at 9:53 AM Krzysztof Kozlowski > > > > wrote: > > > >> On 26/07/2022 20:06, Lad Prabhakar wrote: > > > >>> Ignore the ARM renesas.yaml schema if the board is RZ/Five SMARC EVK > > > >>> (RISC-V arch). > > > >>> > > > >>> Signed-off-by: Lad Prabhakar > > > >>> --- > > > >>> Documentation/devicetree/bindings/arm/renesas.yaml | 9 +++++++++ > > > >>> 1 file changed, 9 insertions(+) > > > >>> > > > >>> diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml > > > >>> index ff80152f092f..f646df1a23af 100644 > > > >>> --- a/Documentation/devicetree/bindings/arm/renesas.yaml > > > >>> +++ b/Documentation/devicetree/bindings/arm/renesas.yaml > > > >>> @@ -9,6 +9,15 @@ title: Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings > > > >>> maintainers: > > > >>> - Geert Uytterhoeven > > > >>> > > > >>> +# We want to ignore this schema if the board is of RISC-V arch > > > >>> +select: > > > >>> + not: > > > >>> + properties: > > > >>> + compatible: > > > >>> + contains: > > > >>> + items: > > > >>> + - const: renesas,r9a07g043f01 > > > >> > > > >> Second issue - why not renesas,r9a07g043? > > > >> > > > > We have two R9A07G043 SOC'S one is based on ARM64 and other on RISC-V. > > > > > > > > RZ/G2UL ARM64: > > > > Type-1 Part Number: R9A07G043U11GBG#BC0 > > > > Type-2 Part Number: R9A07G043U12GBG#BC0 > > > > > > > > RZ/Five RISCV: > > > > 13 x 13 mm Package Part Number: R9A07G043F01GBG#BC0 > > > > > > > > So to differentiate in ARM schema I am using renesas,r9a07g043f01. > > > > > > What is the point to keep then r9a07g043 fallback? The two SoCs are not > > > compatible at all, so they must not use the same fallback. > > > > > Agreed, I wanted to keep it consistent with what was done with ARM64 > > (since both the SoCs shared R9A07G043 part number). > > > > Geert - What are your thoughts on the above? > > "renesas,r9a07g043" is the CPU-less SoC base containing I/O devices. > "renesas,r9a07g043f01", "renesas,r9a07g043u11", and > "renesas,r9a07g043u12" are SoCs built by integrating one or more > RV64 or ARM64 CPU cores and the related interrupt controllers with > the CPU-less SoC base. > That's bang on! which I missed to convenience the DT maintainers. Cheers, Prabhakar _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv